3 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/immap.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 * Low Power Divider specifications
20 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
21 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
23 #define CLOCK_PLL_FVCO_MAX 540000000
24 #define CLOCK_PLL_FVCO_MIN 300000000
26 #define CLOCK_PLL_FSYS_MAX 266666666
27 #define CLOCK_PLL_FSYS_MIN 100000000
30 void clock_enter_limp(int lpdiv)
32 ccm_t *ccm = (ccm_t *)MMAP_CCM;
35 /* Check bounds of divider */
36 if (lpdiv < CLOCK_LPD_MIN)
37 lpdiv = CLOCK_LPD_MIN;
38 if (lpdiv > CLOCK_LPD_MAX)
39 lpdiv = CLOCK_LPD_MAX;
41 /* Round divider down to nearest power of two */
42 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
44 /* Apply the divider to the system clock */
45 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
47 /* Enable Limp Mode */
48 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
52 * brief Exit Limp mode
53 * warning The PLL should be set and locked prior to exiting Limp mode
55 void clock_exit_limp(void)
57 ccm_t *ccm = (ccm_t *)MMAP_CCM;
58 pll_t *pll = (pll_t *)MMAP_PLL;
61 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
63 /* Wait for the PLL to lock */
64 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
69 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
74 ccm_t *ccm = (ccm_t *)MMAP_CCM;
75 pll_t *pll = (pll_t *)MMAP_PLL;
76 int vco, temp, pcrvalue, pfdr;
79 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
80 pfdr = pcrvalue >> 24;
83 bootmode = 0; /* Normal Mode */
86 bootmode = 3; /* Serial Mode */
91 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
92 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
94 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
95 pcrvalue |= 0x1E << 24;
96 out_be32(&pll->pcr, pcrvalue);
98 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
99 CONFIG_SYS_INPUT_CLKSRC;
101 gd->arch.vco_clk = vco; /* Vco clock */
102 } else if (bootmode == 3) {
104 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
105 gd->arch.vco_clk = vco; /* Vco clock */
108 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
111 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
113 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
114 gd->cpu_clk = vco / temp; /* cpu clock */
116 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
117 gd->arch.flb_clk = vco / temp; /* flexbus clock */
118 gd->bus_clk = gd->arch.flb_clk;
121 #ifdef CONFIG_SYS_I2C_FSL
122 gd->arch.i2c1_clk = gd->bus_clk;