3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap.h>
32 #if defined(CONFIG_CMD_NET)
39 * Breath some life into the CPU...
41 * Set up the memory map,
42 * initialize a bunch of registers,
43 * initialize the UPM's
47 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
48 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
49 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
50 volatile scm_t *scm = (scm_t *) MMAP_SCM;
52 /* watchdog is enabled by default - disable the watchdog */
53 #ifndef CONFIG_WATCHDOG
57 scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
59 /* Port configuration */
62 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
63 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
64 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
65 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
68 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
69 gpio->par_cs |= GPIO_PAR_CS_CS1;
70 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
71 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
72 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
75 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
76 gpio->par_cs |= GPIO_PAR_CS_CS2;
77 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
78 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
79 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
82 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
83 gpio->par_cs |= GPIO_PAR_CS_CS3;
84 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
85 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
86 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
89 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
90 gpio->par_cs |= GPIO_PAR_CS_CS4;
91 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
92 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
93 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
96 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
97 gpio->par_cs |= GPIO_PAR_CS_CS5;
98 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
99 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
100 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
103 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
104 gpio->par_cs |= GPIO_PAR_CS_CS6;
105 fbcs->csar6 = CONFIG_SYS_CS6_BASE;
106 fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
107 fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
110 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
111 gpio->par_cs |= GPIO_PAR_CS_CS7;
112 fbcs->csar7 = CONFIG_SYS_CS7_BASE;
113 fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
114 fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
117 #ifdef CONFIG_FSL_I2C
118 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
119 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
126 * initialize higher level parts of CPU like timers
133 void uart_port_conf(int port)
135 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
140 gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
141 gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
145 ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
147 (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
150 #ifdef CONFIG_SYS_UART2_PRI_GPIO
151 gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
152 gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
153 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
155 ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
157 (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
163 #if defined(CONFIG_CMD_NET)
164 int fecpin_setclear(struct eth_device *dev, int setclear)
166 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
170 (GPIO_PAR_FECI2C_EMDC_FECEMDC |
171 GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
174 ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);