3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
14 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/immap.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
30 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
34 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
36 /* we don't return! */
42 char buf1[32], buf2[32];
44 printf("CPU: Freescale Coldfire MCF5208\n"
45 " CPU CLK %s MHz BUS CLK %s MHz\n",
46 strmhz(buf1, gd->cpu_clk),
47 strmhz(buf2, gd->bus_clk));
51 #if defined(CONFIG_WATCHDOG)
52 /* Called by macro WATCHDOG_RESET */
53 void watchdog_reset(void)
55 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
57 out_be16(&wdt->sr, 0x5555);
58 out_be16(&wdt->sr, 0xaaaa);
61 int watchdog_disable(void)
63 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
65 /* reset watchdog counter */
66 out_be16(&wdt->sr, 0x5555);
67 out_be16(&wdt->sr, 0xaaaa);
68 /* disable watchdog timer */
69 out_be16(&wdt->cr, 0);
71 puts("WATCHDOG:disabled\n");
75 int watchdog_init(void)
77 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
79 /* disable watchdog */
80 out_be16(&wdt->cr, 0);
82 /* set timeout and enable watchdog */
84 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
86 /* reset watchdog counter */
87 out_be16(&wdt->sr, 0x5555);
88 out_be16(&wdt->sr, 0xaaaa);
90 puts("WATCHDOG:enabled\n");
93 #endif /* #ifdef CONFIG_WATCHDOG */
94 #endif /* #ifdef CONFIG_M5208 */
98 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
99 * determine which one we are running on, based on the Chip Identification
105 unsigned short cir; /* Chip Identification Register */
106 unsigned short pin; /* Part identification number */
107 unsigned char prn; /* Part revision number */
110 cir = mbar_readShort(MCF_CCM_CIR);
111 pin = cir >> MCF_CCM_CIR_PIN_LEN;
112 prn = cir & MCF_CCM_CIR_PRN_MASK;
115 case MCF_CCM_CIR_PIN_MCF5270:
118 case MCF_CCM_CIR_PIN_MCF5271:
127 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
128 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
130 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
131 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
132 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
137 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
139 /* Call the board specific reset actions first. */
144 mbar_writeByte(MCF_RCM_RCR,
145 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
149 #if defined(CONFIG_WATCHDOG)
150 void watchdog_reset(void)
152 mbar_writeShort(MCF_WTM_WSR, 0x5555);
153 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
156 int watchdog_disable(void)
158 mbar_writeShort(MCF_WTM_WCR, 0);
162 int watchdog_init(void)
164 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
167 #endif /* #ifdef CONFIG_WATCHDOG */
172 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
174 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
176 out_be16(&wdp->wdog_wrrr, 0);
179 /* enable watchdog, set timeout to 0 and wait */
180 out_be16(&wdp->wdog_wrrr, 1);
183 /* we don't return! */
189 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
194 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
204 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
209 printf("Freescale MCF5272 %s\n", suf);
213 #if defined(CONFIG_WATCHDOG)
214 /* Called by macro WATCHDOG_RESET */
215 void watchdog_reset(void)
217 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
219 out_be16(&wdt->wdog_wcr, 0);
222 int watchdog_disable(void)
224 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
226 /* reset watchdog counter */
227 out_be16(&wdt->wdog_wcr, 0);
228 /* disable watchdog interrupt */
229 out_be16(&wdt->wdog_wirr, 0);
230 /* disable watchdog timer */
231 out_be16(&wdt->wdog_wrrr, 0);
233 puts("WATCHDOG:disabled\n");
237 int watchdog_init(void)
239 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
241 /* disable watchdog interrupt */
242 out_be16(&wdt->wdog_wirr, 0);
244 /* set timeout and enable watchdog */
245 out_be16(&wdt->wdog_wrrr,
246 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
248 /* reset watchdog counter */
249 out_be16(&wdt->wdog_wcr, 0);
251 puts("WATCHDOG:enabled\n");
254 #endif /* #ifdef CONFIG_WATCHDOG */
256 #endif /* #ifdef CONFIG_M5272 */
259 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
261 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
265 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
267 /* we don't return! */
275 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
276 strmhz(buf, CONFIG_SYS_CLK));
281 #if defined(CONFIG_WATCHDOG)
282 /* Called by macro WATCHDOG_RESET */
283 void watchdog_reset(void)
285 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
287 out_be16(&wdt->wsr, 0x5555);
288 out_be16(&wdt->wsr, 0xaaaa);
291 int watchdog_disable(void)
293 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
295 /* reset watchdog counter */
296 out_be16(&wdt->wsr, 0x5555);
297 out_be16(&wdt->wsr, 0xaaaa);
299 /* disable watchdog timer */
300 out_be16(&wdt->wcr, 0);
302 puts("WATCHDOG:disabled\n");
306 int watchdog_init(void)
308 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
310 /* disable watchdog */
311 out_be16(&wdt->wcr, 0);
313 /* set timeout and enable watchdog */
315 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
317 /* reset watchdog counter */
318 out_be16(&wdt->wsr, 0x5555);
319 out_be16(&wdt->wsr, 0xaaaa);
321 puts("WATCHDOG:enabled\n");
324 #endif /* #ifdef CONFIG_WATCHDOG */
326 #endif /* #ifdef CONFIG_M5275 */
331 unsigned char resetsource = MCFRESET_RSR;
333 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
334 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
335 printf("Reset:%s%s%s%s%s%s%s\n",
336 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
337 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
338 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
339 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
340 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
341 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
342 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
346 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
348 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
358 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
359 strmhz(buf, CONFIG_SYS_CLK));
363 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
365 /* enable watchdog, set timeout to 0 and wait */
366 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
369 /* we don't return! */
379 unsigned char resetsource = mbar_readLong(SIM_RSR);
380 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
381 strmhz(buf, CONFIG_SYS_CLK));
383 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
384 printf("Reset:%s%s\n",
385 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
387 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
393 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
395 /* enable watchdog, set timeout to 0 and wait */
396 mbar_writeByte(SIM_SYPCR, 0xc0);
399 /* we don't return! */
404 #if defined(CONFIG_MCFFEC)
405 /* Default initializations for MCFFEC controllers. To override,
406 * create a board-specific function called:
407 * int board_eth_init(bd_t *bis)
410 int cpu_eth_init(bd_t *bis)
412 return mcffec_initialize(bis);