3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/immap.h>
38 DECLARE_GLOBAL_DATA_PTR;
41 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
43 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
47 rcm->rcr = RCM_RCR_SOFTRST;
49 /* we don't return! */
55 char buf1[32], buf2[32];
57 printf("CPU: Freescale Coldfire MCF5208\n"
58 " CPU CLK %s MHz BUS CLK %s MHz\n",
59 strmhz(buf1, gd->cpu_clk),
60 strmhz(buf2, gd->bus_clk));
64 #if defined(CONFIG_WATCHDOG)
65 /* Called by macro WATCHDOG_RESET */
66 void watchdog_reset(void)
68 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
73 int watchdog_disable(void)
75 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
77 wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
80 wdt->cr = 0; /* disable watchdog timer */
82 puts("WATCHDOG:disabled\n");
86 int watchdog_init(void)
88 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
90 wdt->cr = 0; /* disable watchdog */
92 /* set timeout and enable watchdog */
94 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
95 wdt->sr = 0x5555; /* reset watchdog counter */
98 puts("WATCHDOG:enabled\n");
101 #endif /* #ifdef CONFIG_WATCHDOG */
102 #endif /* #ifdef CONFIG_M5208 */
106 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
107 * determine which one we are running on, based on the Chip Identification
113 unsigned short cir; /* Chip Identification Register */
114 unsigned short pin; /* Part identification number */
115 unsigned char prn; /* Part revision number */
118 cir = mbar_readShort(MCF_CCM_CIR);
119 pin = cir >> MCF_CCM_CIR_PIN_LEN;
120 prn = cir & MCF_CCM_CIR_PRN_MASK;
123 case MCF_CCM_CIR_PIN_MCF5270:
126 case MCF_CCM_CIR_PIN_MCF5271:
135 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
136 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
138 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
139 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
140 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
145 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
147 /* Call the board specific reset actions first. */
152 mbar_writeByte(MCF_RCM_RCR,
153 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
157 #if defined(CONFIG_WATCHDOG)
158 void watchdog_reset(void)
160 mbar_writeShort(MCF_WTM_WSR, 0x5555);
161 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
164 int watchdog_disable(void)
166 mbar_writeShort(MCF_WTM_WCR, 0);
170 int watchdog_init(void)
172 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
175 #endif /* #ifdef CONFIG_WATCHDOG */
180 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
182 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
187 /* enable watchdog, set timeout to 0 and wait */
191 /* we don't return! */
197 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
202 msk = (sysctrl->sc_dir > 28) & 0xf;
212 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
217 printf("Freescale MCF5272 %s\n", suf);
221 #if defined(CONFIG_WATCHDOG)
222 /* Called by macro WATCHDOG_RESET */
223 void watchdog_reset(void)
225 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
229 int watchdog_disable(void)
231 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
233 wdt->wdog_wcr = 0; /* reset watchdog counter */
234 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
235 wdt->wdog_wrrr = 0; /* disable watchdog timer */
237 puts("WATCHDOG:disabled\n");
241 int watchdog_init(void)
243 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
245 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
247 /* set timeout and enable watchdog */
249 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
250 wdt->wdog_wcr = 0; /* reset watchdog counter */
252 puts("WATCHDOG:enabled\n");
255 #endif /* #ifdef CONFIG_WATCHDOG */
257 #endif /* #ifdef CONFIG_M5272 */
260 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
262 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
266 rcm->rcr = RCM_RCR_SOFTRST;
268 /* we don't return! */
276 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
277 strmhz(buf, CONFIG_SYS_CLK));
282 #if defined(CONFIG_WATCHDOG)
283 /* Called by macro WATCHDOG_RESET */
284 void watchdog_reset(void)
286 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
291 int watchdog_disable(void)
293 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
295 wdt->wsr = 0x5555; /* reset watchdog counter */
297 wdt->wcr = 0; /* disable watchdog timer */
299 puts("WATCHDOG:disabled\n");
303 int watchdog_init(void)
305 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
307 wdt->wcr = 0; /* disable watchdog */
309 /* set timeout and enable watchdog */
311 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
312 wdt->wsr = 0x5555; /* reset watchdog counter */
315 puts("WATCHDOG:enabled\n");
318 #endif /* #ifdef CONFIG_WATCHDOG */
320 #endif /* #ifdef CONFIG_M5275 */
325 unsigned char resetsource = MCFRESET_RSR;
327 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
328 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
329 printf("Reset:%s%s%s%s%s%s%s\n",
330 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
331 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
332 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
333 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
334 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
335 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
336 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
340 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
342 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
352 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
353 strmhz(buf, CONFIG_SYS_CLK));
357 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
359 /* enable watchdog, set timeout to 0 and wait */
360 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
363 /* we don't return! */
373 unsigned char resetsource = mbar_readLong(SIM_RSR);
374 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
375 strmhz(buf, CONFIG_SYS_CLK));
377 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
378 printf("Reset:%s%s\n",
379 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
381 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
387 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
389 /* enable watchdog, set timeout to 0 and wait */
390 mbar_writeByte(SIM_SYPCR, 0xc0);
393 /* we don't return! */
398 #if defined(CONFIG_MCFFEC)
399 /* Default initializations for MCFFEC controllers. To override,
400 * create a board-specific function called:
401 * int board_eth_init(bd_t *bis)
404 int cpu_eth_init(bd_t *bis)
406 return mcffec_initialize(bis);