3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/immap.h>
41 DECLARE_GLOBAL_DATA_PTR;
44 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
46 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
50 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
52 /* we don't return! */
58 char buf1[32], buf2[32];
60 printf("CPU: Freescale Coldfire MCF5208\n"
61 " CPU CLK %s MHz BUS CLK %s MHz\n",
62 strmhz(buf1, gd->cpu_clk),
63 strmhz(buf2, gd->bus_clk));
67 #if defined(CONFIG_WATCHDOG)
68 /* Called by macro WATCHDOG_RESET */
69 void watchdog_reset(void)
71 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
73 out_be16(&wdt->sr, 0x5555);
74 out_be16(&wdt->sr, 0xaaaa);
77 int watchdog_disable(void)
79 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
81 /* reset watchdog counter */
82 out_be16(&wdt->sr, 0x5555);
83 out_be16(&wdt->sr, 0xaaaa);
84 /* disable watchdog timer */
85 out_be16(&wdt->cr, 0);
87 puts("WATCHDOG:disabled\n");
91 int watchdog_init(void)
93 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
95 /* disable watchdog */
96 out_be16(&wdt->cr, 0);
98 /* set timeout and enable watchdog */
100 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
102 /* reset watchdog counter */
103 out_be16(&wdt->sr, 0x5555);
104 out_be16(&wdt->sr, 0xaaaa);
106 puts("WATCHDOG:enabled\n");
109 #endif /* #ifdef CONFIG_WATCHDOG */
110 #endif /* #ifdef CONFIG_M5208 */
114 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
115 * determine which one we are running on, based on the Chip Identification
121 unsigned short cir; /* Chip Identification Register */
122 unsigned short pin; /* Part identification number */
123 unsigned char prn; /* Part revision number */
126 cir = mbar_readShort(MCF_CCM_CIR);
127 pin = cir >> MCF_CCM_CIR_PIN_LEN;
128 prn = cir & MCF_CCM_CIR_PRN_MASK;
131 case MCF_CCM_CIR_PIN_MCF5270:
134 case MCF_CCM_CIR_PIN_MCF5271:
143 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
144 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
146 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
147 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
148 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
153 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
155 /* Call the board specific reset actions first. */
160 mbar_writeByte(MCF_RCM_RCR,
161 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
165 #if defined(CONFIG_WATCHDOG)
166 void watchdog_reset(void)
168 mbar_writeShort(MCF_WTM_WSR, 0x5555);
169 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
172 int watchdog_disable(void)
174 mbar_writeShort(MCF_WTM_WCR, 0);
178 int watchdog_init(void)
180 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
183 #endif /* #ifdef CONFIG_WATCHDOG */
188 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
190 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
192 out_be16(&wdp->wdog_wrrr, 0);
195 /* enable watchdog, set timeout to 0 and wait */
196 out_be16(&wdp->wdog_wrrr, 1);
199 /* we don't return! */
205 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
210 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
220 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
225 printf("Freescale MCF5272 %s\n", suf);
229 #if defined(CONFIG_WATCHDOG)
230 /* Called by macro WATCHDOG_RESET */
231 void watchdog_reset(void)
233 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
235 out_be16(&wdt->wdog_wcr, 0);
238 int watchdog_disable(void)
240 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
242 /* reset watchdog counter */
243 out_be16(&wdt->wdog_wcr, 0);
244 /* disable watchdog interrupt */
245 out_be16(&wdt->wdog_wirr, 0);
246 /* disable watchdog timer */
247 out_be16(&wdt->wdog_wrrr, 0);
249 puts("WATCHDOG:disabled\n");
253 int watchdog_init(void)
255 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
257 /* disable watchdog interrupt */
258 out_be16(&wdt->wdog_wirr, 0);
260 /* set timeout and enable watchdog */
261 out_be16(&wdt->wdog_wrrr,
262 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
264 /* reset watchdog counter */
265 out_be16(&wdt->wdog_wcr, 0);
267 puts("WATCHDOG:enabled\n");
270 #endif /* #ifdef CONFIG_WATCHDOG */
272 #endif /* #ifdef CONFIG_M5272 */
275 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
277 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
281 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
283 /* we don't return! */
291 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
292 strmhz(buf, CONFIG_SYS_CLK));
297 #if defined(CONFIG_WATCHDOG)
298 /* Called by macro WATCHDOG_RESET */
299 void watchdog_reset(void)
301 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
303 out_be16(&wdt->wsr, 0x5555);
304 out_be16(&wdt->wsr, 0xaaaa);
307 int watchdog_disable(void)
309 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
311 /* reset watchdog counter */
312 out_be16(&wdt->wsr, 0x5555);
313 out_be16(&wdt->wsr, 0xaaaa);
315 /* disable watchdog timer */
316 out_be16(&wdt->wcr, 0);
318 puts("WATCHDOG:disabled\n");
322 int watchdog_init(void)
324 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
326 /* disable watchdog */
327 out_be16(&wdt->wcr, 0);
329 /* set timeout and enable watchdog */
331 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
333 /* reset watchdog counter */
334 out_be16(&wdt->wsr, 0x5555);
335 out_be16(&wdt->wsr, 0xaaaa);
337 puts("WATCHDOG:enabled\n");
340 #endif /* #ifdef CONFIG_WATCHDOG */
342 #endif /* #ifdef CONFIG_M5275 */
347 unsigned char resetsource = MCFRESET_RSR;
349 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
350 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
351 printf("Reset:%s%s%s%s%s%s%s\n",
352 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
353 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
354 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
355 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
356 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
357 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
358 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
362 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
364 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
374 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
375 strmhz(buf, CONFIG_SYS_CLK));
379 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
381 /* enable watchdog, set timeout to 0 and wait */
382 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
385 /* we don't return! */
395 unsigned char resetsource = mbar_readLong(SIM_RSR);
396 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
397 strmhz(buf, CONFIG_SYS_CLK));
399 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
400 printf("Reset:%s%s\n",
401 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
403 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
409 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
411 /* enable watchdog, set timeout to 0 and wait */
412 mbar_writeByte(SIM_SYPCR, 0xc0);
415 /* we don't return! */
420 #if defined(CONFIG_MCFFEC)
421 /* Default initializations for MCFFEC controllers. To override,
422 * create a board-specific function called:
423 * int board_eth_init(bd_t *bis)
426 int cpu_eth_init(bd_t *bis)
428 return mcffec_initialize(bis);