1 // SPDX-License-Identifier: GPL-2.0+
4 * Josef Baumgartner <josef.baumgartner@telex.de>
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
13 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
19 #include <asm/immap.h>
24 DECLARE_GLOBAL_DATA_PTR;
27 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
29 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
33 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
35 /* we don't return! */
39 #if defined(CONFIG_DISPLAY_CPUINFO)
40 int print_cpuinfo(void)
42 char buf1[32], buf2[32];
44 printf("CPU: Freescale Coldfire MCF5208\n"
45 " CPU CLK %s MHz BUS CLK %s MHz\n",
46 strmhz(buf1, gd->cpu_clk),
47 strmhz(buf2, gd->bus_clk));
50 #endif /* CONFIG_DISPLAY_CPUINFO */
52 #if defined(CONFIG_WATCHDOG)
53 /* Called by macro WATCHDOG_RESET */
54 void watchdog_reset(void)
56 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
58 out_be16(&wdt->sr, 0x5555);
59 out_be16(&wdt->sr, 0xaaaa);
62 int watchdog_disable(void)
64 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
66 /* reset watchdog counter */
67 out_be16(&wdt->sr, 0x5555);
68 out_be16(&wdt->sr, 0xaaaa);
69 /* disable watchdog timer */
70 out_be16(&wdt->cr, 0);
72 puts("WATCHDOG:disabled\n");
76 int watchdog_init(void)
78 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
80 /* disable watchdog */
81 out_be16(&wdt->cr, 0);
83 /* set timeout and enable watchdog */
85 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
87 /* reset watchdog counter */
88 out_be16(&wdt->sr, 0x5555);
89 out_be16(&wdt->sr, 0xaaaa);
91 puts("WATCHDOG:enabled\n");
94 #endif /* #ifdef CONFIG_WATCHDOG */
95 #endif /* #ifdef CONFIG_M5208 */
98 #if defined(CONFIG_DISPLAY_CPUINFO)
100 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
101 * determine which one we are running on, based on the Chip Identification
104 int print_cpuinfo(void)
107 unsigned short cir; /* Chip Identification Register */
108 unsigned short pin; /* Part identification number */
109 unsigned char prn; /* Part revision number */
112 cir = mbar_readShort(MCF_CCM_CIR);
113 pin = cir >> MCF_CCM_CIR_PIN_LEN;
114 prn = cir & MCF_CCM_CIR_PRN_MASK;
117 case MCF_CCM_CIR_PIN_MCF5270:
120 case MCF_CCM_CIR_PIN_MCF5271:
129 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
130 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
132 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
133 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
134 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
138 #endif /* CONFIG_DISPLAY_CPUINFO */
140 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
142 /* Call the board specific reset actions first. */
147 mbar_writeByte(MCF_RCM_RCR,
148 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
152 #if defined(CONFIG_WATCHDOG)
153 void watchdog_reset(void)
155 mbar_writeShort(MCF_WTM_WSR, 0x5555);
156 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
159 int watchdog_disable(void)
161 mbar_writeShort(MCF_WTM_WCR, 0);
165 int watchdog_init(void)
167 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
170 #endif /* #ifdef CONFIG_WATCHDOG */
175 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
177 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
179 out_be16(&wdp->wdog_wrrr, 0);
182 /* enable watchdog, set timeout to 0 and wait */
183 out_be16(&wdp->wdog_wrrr, 1);
186 /* we don't return! */
190 #if defined(CONFIG_DISPLAY_CPUINFO)
191 int print_cpuinfo(void)
193 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
198 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
208 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
213 printf("Freescale MCF5272 %s\n", suf);
216 #endif /* CONFIG_DISPLAY_CPUINFO */
218 #if defined(CONFIG_WATCHDOG)
219 /* Called by macro WATCHDOG_RESET */
220 void watchdog_reset(void)
222 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
224 out_be16(&wdt->wdog_wcr, 0);
227 int watchdog_disable(void)
229 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
231 /* reset watchdog counter */
232 out_be16(&wdt->wdog_wcr, 0);
233 /* disable watchdog interrupt */
234 out_be16(&wdt->wdog_wirr, 0);
235 /* disable watchdog timer */
236 out_be16(&wdt->wdog_wrrr, 0);
238 puts("WATCHDOG:disabled\n");
242 int watchdog_init(void)
244 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
246 /* disable watchdog interrupt */
247 out_be16(&wdt->wdog_wirr, 0);
249 /* set timeout and enable watchdog */
250 out_be16(&wdt->wdog_wrrr,
251 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
253 /* reset watchdog counter */
254 out_be16(&wdt->wdog_wcr, 0);
256 puts("WATCHDOG:enabled\n");
259 #endif /* #ifdef CONFIG_WATCHDOG */
261 #endif /* #ifdef CONFIG_M5272 */
264 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
266 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
270 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
272 /* we don't return! */
276 #if defined(CONFIG_DISPLAY_CPUINFO)
277 int print_cpuinfo(void)
281 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
282 strmhz(buf, CONFIG_SYS_CLK));
285 #endif /* CONFIG_DISPLAY_CPUINFO */
287 #if defined(CONFIG_WATCHDOG)
288 /* Called by macro WATCHDOG_RESET */
289 void watchdog_reset(void)
291 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
293 out_be16(&wdt->wsr, 0x5555);
294 out_be16(&wdt->wsr, 0xaaaa);
297 int watchdog_disable(void)
299 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
301 /* reset watchdog counter */
302 out_be16(&wdt->wsr, 0x5555);
303 out_be16(&wdt->wsr, 0xaaaa);
305 /* disable watchdog timer */
306 out_be16(&wdt->wcr, 0);
308 puts("WATCHDOG:disabled\n");
312 int watchdog_init(void)
314 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
316 /* disable watchdog */
317 out_be16(&wdt->wcr, 0);
319 /* set timeout and enable watchdog */
321 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
323 /* reset watchdog counter */
324 out_be16(&wdt->wsr, 0x5555);
325 out_be16(&wdt->wsr, 0xaaaa);
327 puts("WATCHDOG:enabled\n");
330 #endif /* #ifdef CONFIG_WATCHDOG */
332 #endif /* #ifdef CONFIG_M5275 */
335 #if defined(CONFIG_DISPLAY_CPUINFO)
336 int print_cpuinfo(void)
338 unsigned char resetsource = MCFRESET_RSR;
340 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
341 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
342 printf("Reset:%s%s%s%s%s%s%s\n",
343 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
344 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
345 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
346 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
347 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
348 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
349 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
352 #endif /* CONFIG_DISPLAY_CPUINFO */
354 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
356 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
362 #if defined(CONFIG_DISPLAY_CPUINFO)
363 int print_cpuinfo(void)
367 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
368 strmhz(buf, CONFIG_SYS_CLK));
371 #endif /* CONFIG_DISPLAY_CPUINFO */
373 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
375 /* enable watchdog, set timeout to 0 and wait */
376 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
379 /* we don't return! */
385 #if defined(CONFIG_DISPLAY_CPUINFO)
386 int print_cpuinfo(void)
390 unsigned char resetsource = mbar_readLong(SIM_RSR);
391 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
392 strmhz(buf, CONFIG_SYS_CLK));
394 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
395 printf("Reset:%s%s\n",
396 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
398 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
403 #endif /* CONFIG_DISPLAY_CPUINFO */
405 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
407 /* enable watchdog, set timeout to 0 and wait */
408 mbar_writeByte(SIM_SYPCR, 0xc0);
411 /* we don't return! */
416 #if defined(CONFIG_MCFFEC)
417 /* Default initializations for MCFFEC controllers. To override,
418 * create a board-specific function called:
419 * int board_eth_init(bd_t *bis)
422 int cpu_eth_init(bd_t *bis)
424 return mcffec_initialize(bis);