3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
14 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/immap.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
30 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
34 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
36 /* we don't return! */
40 #if defined(CONFIG_DISPLAY_CPUINFO)
41 int print_cpuinfo(void)
43 char buf1[32], buf2[32];
45 printf("CPU: Freescale Coldfire MCF5208\n"
46 " CPU CLK %s MHz BUS CLK %s MHz\n",
47 strmhz(buf1, gd->cpu_clk),
48 strmhz(buf2, gd->bus_clk));
51 #endif /* CONFIG_DISPLAY_CPUINFO */
53 #if defined(CONFIG_WATCHDOG)
54 /* Called by macro WATCHDOG_RESET */
55 void watchdog_reset(void)
57 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
59 out_be16(&wdt->sr, 0x5555);
60 out_be16(&wdt->sr, 0xaaaa);
63 int watchdog_disable(void)
65 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
67 /* reset watchdog counter */
68 out_be16(&wdt->sr, 0x5555);
69 out_be16(&wdt->sr, 0xaaaa);
70 /* disable watchdog timer */
71 out_be16(&wdt->cr, 0);
73 puts("WATCHDOG:disabled\n");
77 int watchdog_init(void)
79 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
81 /* disable watchdog */
82 out_be16(&wdt->cr, 0);
84 /* set timeout and enable watchdog */
86 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
88 /* reset watchdog counter */
89 out_be16(&wdt->sr, 0x5555);
90 out_be16(&wdt->sr, 0xaaaa);
92 puts("WATCHDOG:enabled\n");
95 #endif /* #ifdef CONFIG_WATCHDOG */
96 #endif /* #ifdef CONFIG_M5208 */
99 #if defined(CONFIG_DISPLAY_CPUINFO)
101 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
102 * determine which one we are running on, based on the Chip Identification
105 int print_cpuinfo(void)
108 unsigned short cir; /* Chip Identification Register */
109 unsigned short pin; /* Part identification number */
110 unsigned char prn; /* Part revision number */
113 cir = mbar_readShort(MCF_CCM_CIR);
114 pin = cir >> MCF_CCM_CIR_PIN_LEN;
115 prn = cir & MCF_CCM_CIR_PRN_MASK;
118 case MCF_CCM_CIR_PIN_MCF5270:
121 case MCF_CCM_CIR_PIN_MCF5271:
130 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
131 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
133 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
134 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
135 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
139 #endif /* CONFIG_DISPLAY_CPUINFO */
141 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
143 /* Call the board specific reset actions first. */
148 mbar_writeByte(MCF_RCM_RCR,
149 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
153 #if defined(CONFIG_WATCHDOG)
154 void watchdog_reset(void)
156 mbar_writeShort(MCF_WTM_WSR, 0x5555);
157 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
160 int watchdog_disable(void)
162 mbar_writeShort(MCF_WTM_WCR, 0);
166 int watchdog_init(void)
168 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
171 #endif /* #ifdef CONFIG_WATCHDOG */
176 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
178 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
180 out_be16(&wdp->wdog_wrrr, 0);
183 /* enable watchdog, set timeout to 0 and wait */
184 out_be16(&wdp->wdog_wrrr, 1);
187 /* we don't return! */
191 #if defined(CONFIG_DISPLAY_CPUINFO)
192 int print_cpuinfo(void)
194 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
199 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
209 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
214 printf("Freescale MCF5272 %s\n", suf);
217 #endif /* CONFIG_DISPLAY_CPUINFO */
219 #if defined(CONFIG_WATCHDOG)
220 /* Called by macro WATCHDOG_RESET */
221 void watchdog_reset(void)
223 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
225 out_be16(&wdt->wdog_wcr, 0);
228 int watchdog_disable(void)
230 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
232 /* reset watchdog counter */
233 out_be16(&wdt->wdog_wcr, 0);
234 /* disable watchdog interrupt */
235 out_be16(&wdt->wdog_wirr, 0);
236 /* disable watchdog timer */
237 out_be16(&wdt->wdog_wrrr, 0);
239 puts("WATCHDOG:disabled\n");
243 int watchdog_init(void)
245 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
247 /* disable watchdog interrupt */
248 out_be16(&wdt->wdog_wirr, 0);
250 /* set timeout and enable watchdog */
251 out_be16(&wdt->wdog_wrrr,
252 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
254 /* reset watchdog counter */
255 out_be16(&wdt->wdog_wcr, 0);
257 puts("WATCHDOG:enabled\n");
260 #endif /* #ifdef CONFIG_WATCHDOG */
262 #endif /* #ifdef CONFIG_M5272 */
265 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
267 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
271 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
273 /* we don't return! */
277 #if defined(CONFIG_DISPLAY_CPUINFO)
278 int print_cpuinfo(void)
282 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
283 strmhz(buf, CONFIG_SYS_CLK));
286 #endif /* CONFIG_DISPLAY_CPUINFO */
288 #if defined(CONFIG_WATCHDOG)
289 /* Called by macro WATCHDOG_RESET */
290 void watchdog_reset(void)
292 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
294 out_be16(&wdt->wsr, 0x5555);
295 out_be16(&wdt->wsr, 0xaaaa);
298 int watchdog_disable(void)
300 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
302 /* reset watchdog counter */
303 out_be16(&wdt->wsr, 0x5555);
304 out_be16(&wdt->wsr, 0xaaaa);
306 /* disable watchdog timer */
307 out_be16(&wdt->wcr, 0);
309 puts("WATCHDOG:disabled\n");
313 int watchdog_init(void)
315 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
317 /* disable watchdog */
318 out_be16(&wdt->wcr, 0);
320 /* set timeout and enable watchdog */
322 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
324 /* reset watchdog counter */
325 out_be16(&wdt->wsr, 0x5555);
326 out_be16(&wdt->wsr, 0xaaaa);
328 puts("WATCHDOG:enabled\n");
331 #endif /* #ifdef CONFIG_WATCHDOG */
333 #endif /* #ifdef CONFIG_M5275 */
336 #if defined(CONFIG_DISPLAY_CPUINFO)
337 int print_cpuinfo(void)
339 unsigned char resetsource = MCFRESET_RSR;
341 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
342 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
343 printf("Reset:%s%s%s%s%s%s%s\n",
344 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
345 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
346 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
347 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
348 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
349 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
350 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
353 #endif /* CONFIG_DISPLAY_CPUINFO */
355 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
357 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
363 #if defined(CONFIG_DISPLAY_CPUINFO)
364 int print_cpuinfo(void)
368 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
369 strmhz(buf, CONFIG_SYS_CLK));
372 #endif /* CONFIG_DISPLAY_CPUINFO */
374 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
376 /* enable watchdog, set timeout to 0 and wait */
377 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
380 /* we don't return! */
386 #if defined(CONFIG_DISPLAY_CPUINFO)
387 int print_cpuinfo(void)
391 unsigned char resetsource = mbar_readLong(SIM_RSR);
392 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
393 strmhz(buf, CONFIG_SYS_CLK));
395 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
396 printf("Reset:%s%s\n",
397 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
399 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
404 #endif /* CONFIG_DISPLAY_CPUINFO */
406 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
408 /* enable watchdog, set timeout to 0 and wait */
409 mbar_writeByte(SIM_SYPCR, 0xc0);
412 /* we don't return! */
417 #if defined(CONFIG_MCFFEC)
418 /* Default initializations for MCFFEC controllers. To override,
419 * create a board-specific function called:
420 * int board_eth_init(bd_t *bis)
423 int cpu_eth_init(bd_t *bis)
425 return mcffec_initialize(bis);