1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 #include <asm/processor.h>
14 #include <asm/immap.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* PLL min/max specifications */
20 #define MAX_FVCO 500000 /* KHz */
21 #define MAX_FSYS 80000 /* KHz */
22 #define MIN_FSYS 58333 /* KHz */
24 #ifdef CONFIG_MCF5301x
25 #define FREF 20000 /* KHz */
26 #define MAX_MFD 63 /* Multiplier */
27 #define MIN_MFD 0 /* Multiplier */
30 /* Low Power Divider specifications */
31 #define MIN_LPD (0) /* Divider (not encoded) */
32 #define MAX_LPD (15) /* Divider (not encoded) */
33 #define DEFAULT_LPD (0) /* Divider (not encoded) */
37 #define FREF 16000 /* KHz */
38 #define MAX_MFD 135 /* Multiplier */
39 #define MIN_MFD 88 /* Multiplier */
41 /* Low Power Divider specifications */
42 #define MIN_LPD (1 << 0) /* Divider (not encoded) */
43 #define MAX_LPD (1 << 15) /* Divider (not encoded) */
44 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
47 #define BUSDIV 6 /* Divider */
49 /* Get the value of the current system clock */
50 int get_sys_clock(void)
52 ccm_t *ccm = (ccm_t *)(MMAP_CCM);
53 pll_t *pll = (pll_t *)(MMAP_PLL);
56 /* Test to see if device is in LIMP mode */
57 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
59 #ifdef CONFIG_MCF5301x
60 return (FREF / (3 * (1 << divider)));
63 return (FREF / (2 << divider));
66 #ifdef CONFIG_MCF5301x
67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
68 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
69 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
71 return (((FREF * pfdr) / refdiv) / busdiv);
74 return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
80 * Initialize the Low Power Divider circuit
83 * div Desired system frequency divider
86 * The resulting output system frequency
88 int clock_limp(int div)
90 ccm_t *ccm = (ccm_t *)(MMAP_CCM);
93 /* Check bounds of divider */
99 /* Save of the current value of the SSIDIV so we don't overwrite the value */
100 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
102 /* Apply the divider to the system clock */
103 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
105 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
107 return (FREF / (3 * (1 << div)));
110 /* Exit low power LIMP mode */
111 int clock_exit_limp(void)
113 ccm_t *ccm = (ccm_t *)(MMAP_CCM);
117 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
119 /* Wait for PLL to lock */
120 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
123 fout = get_sys_clock();
128 /* Initialize the PLL
131 * fref PLL reference clock frequency in KHz
132 * fsys Desired PLL output frequency in KHz
133 * flags Operating parameters
136 * The resulting output system frequency
138 int clock_pll(int fsys, int flags)
140 #ifdef CONFIG_MCF532x
141 u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
143 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
144 pll_t *pll = (pll_t *)(MMAP_PLL);
145 int fref, temp, fout, mfd;
151 /* Return current PLL output */
152 #ifdef CONFIG_MCF5301x
153 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
154 mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
156 return (fref * mfd) / busdiv;
158 #ifdef CONFIG_MCF532x
159 mfd = in_8(&pll->pfdr);
161 return (fref * mfd / (BUSDIV * 4));
165 /* Check bounds of requested system clock */
173 * Multiplying by 100 when calculating the temp value,
174 * and then dividing by 100 to calculate the mfd allows
175 * for exact values without needing to include floating
178 temp = (100 * fsys) / fref;
179 #ifdef CONFIG_MCF5301x
180 mfd = (BUSDIV * temp) / 100;
182 /* Determine the output frequency for selected values */
183 fout = ((fref * mfd) / BUSDIV);
185 #ifdef CONFIG_MCF532x
186 mfd = (4 * BUSDIV * temp) / 100;
188 /* Determine the output frequency for selected values */
189 fout = ((fref * mfd) / (BUSDIV * 4));
192 /* must not tamper with SDRAMC if running from SDRAM */
193 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
195 * Check to see if the SDRAM has already been initialized.
196 * If it has then the SDRAM needs to be put into self refresh
197 * mode before reprogramming the PLL.
199 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
200 clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
203 * Initialize the PLL to generate the new system clock frequency.
204 * The device must be put into LIMP mode to reprogram the PLL.
207 /* Enter LIMP mode */
208 clock_limp(DEFAULT_LPD);
210 #ifdef CONFIG_MCF5301x
212 PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
213 PLL_PDR_OUTDIV2(BUSDIV - 1) |
214 PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
215 PLL_PDR_OUTDIV4(USBDIV - 1));
217 clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
218 setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
220 #ifdef CONFIG_MCF532x
221 /* Reprogram PLL for desired fsys */
223 PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
225 out_8(&pll->pfdr, mfd);
231 /* Return the SDRAM to normal operation if it is in use. */
232 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
233 setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
235 #ifdef CONFIG_MCF532x
237 * software workaround for SDRAM opeartion after exiting LIMP
240 out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
243 /* wait for DQS logic to relock */
244 for (i = 0; i < 0x200; i++) ;
245 #endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
250 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
253 gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
254 gd->cpu_clk = (gd->bus_clk * 3);
256 #ifdef CONFIG_SYS_I2C_FSL
257 gd->arch.i2c1_clk = gd->bus_clk;