2 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * PCI Configuration space access support
30 #include <asm/immap.h>
32 #if defined(CONFIG_PCI)
33 /* System RAM mapped over PCI */
34 #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
35 #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
36 #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
38 #define cfg_read(val, addr, type, op) *val = op((type)(addr));
39 #define cfg_write(val, addr, type, op) op((type *)(addr), (val));
41 #define PCI_OP(rw, size, type, op, mask) \
42 int pci_##rw##_cfg_##size(struct pci_controller *hose, \
43 pci_dev_t dev, int offset, type val) \
47 addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
48 out_be32(hose->cfg_addr, addr); \
49 cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
50 out_be32(hose->cfg_addr, addr & 0x7fffffff); \
54 PCI_OP(read, byte, u8 *, in_8, 3)
55 PCI_OP(read, word, u16 *, in_le16, 2)
56 PCI_OP(read, dword, u32 *, in_le32, 0)
57 PCI_OP(write, byte, u8, out_8, 3)
58 PCI_OP(write, word, u16, out_le16, 2)
59 PCI_OP(write, dword, u32, out_le32, 0)
61 void pci_mcf5445x_init(struct pci_controller *hose)
63 pci_t *pci = (pci_t *)MMAP_PCI;
64 pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
65 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
68 out_be32(&pciarb->acr, 0x001f001f);
70 /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
72 out_be16(&gpio->par_pci,
73 GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
74 GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
75 GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
76 GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
78 /* Assert reset bit */
79 setbits_be32(&pci->gscr, PCI_GSCR_PR);
81 setbits_be32(&pci->tcr1, PCI_TCR1_P);
83 /* Initiator windows */
84 out_be32(&pci->iw0btar,
85 CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
86 out_be32(&pci->iw1btar,
87 CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
88 out_be32(&pci->iw2btar,
89 CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
92 PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
93 PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
95 out_be32(&pci->icr, 0);
97 /* Enable bus master and mem access */
98 out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
100 /* Cache line size and master latency */
101 out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
102 out_be32(&pci->cr2, 0);
104 #ifdef CONFIG_SYS_PCI_BAR0
105 out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
106 out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
107 barEn |= PCI_TCR2_B0E;
109 #ifdef CONFIG_SYS_PCI_BAR1
110 out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
111 out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
112 barEn |= PCI_TCR2_B1E;
114 #ifdef CONFIG_SYS_PCI_BAR2
115 out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
116 out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
117 barEn |= PCI_TCR2_B2E;
119 #ifdef CONFIG_SYS_PCI_BAR3
120 out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
121 out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
122 barEn |= PCI_TCR2_B3E;
124 #ifdef CONFIG_SYS_PCI_BAR4
125 out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
126 out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
127 barEn |= PCI_TCR2_B4E;
129 #ifdef CONFIG_SYS_PCI_BAR5
130 out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
131 out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
132 barEn |= PCI_TCR2_B5E;
135 out_be32(&pci->tcr2, barEn);
137 /* Deassert reset bit */
138 clrbits_be32(&pci->gscr, PCI_GSCR_PR);
141 /* Enable PCI bus master support */
142 hose->first_busno = 0;
143 hose->last_busno = 0xff;
145 pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
146 CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
148 pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
149 CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
151 pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
152 CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
153 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
155 hose->region_count = 3;
157 hose->cfg_addr = &(pci->car);
158 hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
160 pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
161 pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
162 pci_write_cfg_dword);
165 pci_register_hose(hose);
166 hose->last_busno = pci_hose_scan(hose);
168 #endif /* CONFIG_PCI */