3 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap.h>
31 DECLARE_GLOBAL_DATA_PTR;
34 * Low Power Divider specifications
36 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
37 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
39 #define CLOCK_PLL_FVCO_MAX 540000000
40 #define CLOCK_PLL_FVCO_MIN 300000000
42 #define CLOCK_PLL_FSYS_MAX 266666666
43 #define CLOCK_PLL_FSYS_MIN 100000000
46 void clock_enter_limp(int lpdiv)
48 ccm_t *ccm = (ccm_t *)MMAP_CCM;
51 /* Check bounds of divider */
52 if (lpdiv < CLOCK_LPD_MIN)
53 lpdiv = CLOCK_LPD_MIN;
54 if (lpdiv > CLOCK_LPD_MAX)
55 lpdiv = CLOCK_LPD_MAX;
57 /* Round divider down to nearest power of two */
58 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
60 #ifdef CONFIG_MCF5445x
61 /* Apply the divider to the system clock */
62 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
65 /* Enable Limp Mode */
66 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
70 * brief Exit Limp mode
71 * warning The PLL should be set and locked prior to exiting Limp mode
73 void clock_exit_limp(void)
75 ccm_t *ccm = (ccm_t *)MMAP_CCM;
76 pll_t *pll = (pll_t *)MMAP_PLL;
79 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
81 /* Wait for the PLL to lock */
82 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
86 #ifdef CONFIG_MCF5441x
87 void setup_5441x_clocks(void)
89 ccm_t *ccm = (ccm_t *)MMAP_CCM;
90 pll_t *pll = (pll_t *)MMAP_PLL;
91 int temp, vco = 0, bootmod_ccr, pdr;
93 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
95 switch (bootmod_ccr) {
97 out_be32(&pll->pcr, 0x00000013);
98 out_be32(&pll->pdr, 0x00e70c61);
107 /*Change frequency for Modelo SER1 USB host*/
108 #ifdef CONFIG_LOW_MCFCLK
109 temp = in_be32(&pll->pcr);
112 out_be32(&pll->pcr, temp);
114 temp = in_be32(&pll->pdr);
117 out_be32(&pll->pdr, temp);
121 setbits_be16(&ccm->misccr2, 0x02);
123 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
124 CONFIG_SYS_INPUT_CLKSRC;
127 gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
129 pdr = in_be32(&pll->pdr);
130 temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
131 gd->cpu_clk = vco / temp; /* cpu clock */
132 gd->flb_clk = vco / temp; /* FlexBus clock */
134 if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
137 temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
138 gd->bus_clk = vco / temp; /* bus clock */
143 #ifdef CONFIG_MCF5445x
144 void setup_5445x_clocks(void)
146 ccm_t *ccm = (ccm_t *)MMAP_CCM;
147 pll_t *pll = (pll_t *)MMAP_PLL;
148 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
149 int pllmult_pci[] = { 12, 6, 16, 8 };
150 int vco = 0, temp, fbtemp, pcrvalue;
151 int *pPllmult = NULL;
157 #ifdef CONFIG_M54455EVB
158 u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
162 /* To determine PCI is present or not */
163 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
164 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
165 pPllmult = &pllmult_pci[0];
166 fbpll_mask = 3; /* 11b */
171 pPllmult = &pllmult_nopci[0];
172 fbpll_mask = 7; /* 111b */
179 #ifdef CONFIG_M54455EVB
180 bootmode = (in_8(cpld) & 0x03);
183 /* Temporary read from CCR- fixed fb issue, must be the same clock
184 as pci or input clock, causing cpld/fpga read inconsistancy */
185 fbtemp = pPllmult[ccm->ccr & fbpll_mask];
187 /* Break down into small pieces, code still in flex bus */
188 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
190 pcrvalue |= PLL_PCR_OUTDIV3(temp);
192 out_be32(&pll->pcr, pcrvalue);
195 #ifdef CONFIG_M54451EVB
196 /* No external logic to read the bootmode, hard coded from built */
202 /* default value is 16 mul, set to 20 mul */
203 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
204 out_be32(&pll->pcr, pcrvalue);
205 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
212 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
214 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
215 /* invaild range, re-set in PCR */
216 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
219 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
220 for (i = j; i < 0xFF; i++) {
221 vco = i * CONFIG_SYS_INPUT_CLKSRC;
222 if (vco >= CLOCK_PLL_FVCO_MIN) {
224 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
230 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
231 fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
232 pcrvalue |= ((i << 24) | fbtemp);
234 out_be32(&pll->pcr, pcrvalue);
236 gd->vco_clk = vco; /* Vco clock */
237 } else if (bootmode == 2) {
239 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
240 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
242 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
243 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
244 out_be32(&pll->pcr, pcrvalue);
245 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
247 gd->vco_clk = vco; /* Vco clock */
248 } else if (bootmode == 3) {
250 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
251 gd->vco_clk = vco; /* Vco clock */
254 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
257 gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
259 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
260 gd->cpu_clk = vco / temp; /* cpu clock */
262 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
263 gd->bus_clk = vco / temp; /* bus clock */
265 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
266 gd->flb_clk = vco / temp; /* FlexBus clock */
270 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
271 gd->pci_clk = vco / temp; /* PCI clock */
276 #ifdef CONFIG_FSL_I2C
277 gd->i2c1_clk = gd->bus_clk;
282 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
285 #ifdef CONFIG_MCF5441x
286 setup_5441x_clocks();
288 #ifdef CONFIG_MCF5445x
289 setup_5445x_clocks();
292 #ifdef CONFIG_FSL_I2C
293 gd->i2c1_clk = gd->bus_clk;