2 * FlexBus Internal Memory Map
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /*********************************************************************
30 * FlexBus Chip Selects (FBCS)
31 *********************************************************************/
34 u16 csar0; /* Chip-select Address */
36 u32 csmr0; /* Chip-select Mask */
38 u16 cscr0; /* Chip-select Control */
84 u32 csar0; /* Chip-select Address */
85 u32 csmr0; /* Chip-select Mask */
86 u32 cscr0; /* Chip-select Control */
111 #define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
113 #define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16)
114 #define FBCS_CSMR_BAM_MASK (0x0000FFFF)
115 #define FBCS_CSMR_BAM_4G (0xFFFF0000)
116 #define FBCS_CSMR_BAM_2G (0x7FFF0000)
117 #define FBCS_CSMR_BAM_1G (0x3FFF0000)
118 #define FBCS_CSMR_BAM_1024M (0x3FFF0000)
119 #define FBCS_CSMR_BAM_512M (0x1FFF0000)
120 #define FBCS_CSMR_BAM_256M (0x0FFF0000)
121 #define FBCS_CSMR_BAM_128M (0x07FF0000)
122 #define FBCS_CSMR_BAM_64M (0x03FF0000)
123 #define FBCS_CSMR_BAM_32M (0x01FF0000)
124 #define FBCS_CSMR_BAM_16M (0x00FF0000)
125 #define FBCS_CSMR_BAM_8M (0x007F0000)
126 #define FBCS_CSMR_BAM_4M (0x003F0000)
127 #define FBCS_CSMR_BAM_2M (0x001F0000)
128 #define FBCS_CSMR_BAM_1M (0x000F0000)
129 #define FBCS_CSMR_BAM_1024K (0x000F0000)
130 #define FBCS_CSMR_BAM_512K (0x00070000)
131 #define FBCS_CSMR_BAM_256K (0x00030000)
132 #define FBCS_CSMR_BAM_128K (0x00010000)
133 #define FBCS_CSMR_BAM_64K (0x00000000)
136 #define FBCS_CSMR_WP (0x00000080)
137 #define FBCS_CSMR_AM (0x00000040)
138 #define FBCS_CSMR_CI (0x00000020)
139 #define FBCS_CSMR_SC (0x00000010)
140 #define FBCS_CSMR_SD (0x00000008)
141 #define FBCS_CSMR_UC (0x00000004)
142 #define FBCS_CSMR_UD (0x00000002)
144 #define FBCS_CSMR_WP (0x00000100)
146 #define FBCS_CSMR_V (0x00000001) /* Valid bit */
149 #define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14)
150 #define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10)
151 #define FBCS_CSCR_AA_ON (1 << 8)
152 #define FBCS_CSCR_AA_OFF (0 << 8)
153 #define FBCS_CSCR_PS_32 (0 << 6)
154 #define FBCS_CSCR_PS_16 (2 << 6)
155 #define FBCS_CSCR_PS_8 (1 << 6)
156 #define FBCS_CSCR_BEM_ON (1 << 5)
157 #define FBCS_CSCR_BEM_OFF (0 << 5)
158 #define FBCS_CSCR_BSTR_ON (1 << 4)
159 #define FBCS_CSCR_BSTR_OFF (0 << 4)
160 #define FBCS_CSCR_BSTW_ON (1 << 3)
161 #define FBCS_CSCR_BSTW_OFF (0 << 3)
162 #define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0)
164 #define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
165 #define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
166 #define FBCS_CSCR_SWSEN (0x00800000)
167 #define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20)
168 #define FBCS_CSCR_ASET_MASK (0xFFCFFFFF)
169 #define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18)
170 #define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF)
171 #define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16)
172 #define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF)
173 #define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10)
174 #define FBCS_CSCR_WS_MASK (0xFFFF03FF)
175 #define FBCS_CSCR_SBM (0x00000200)
176 #define FBCS_CSCR_AA (0x00000100)
177 #define FBCS_CSCR_PS(x) (((x) & 0x03) << 6)
178 #define FBCS_CSCR_PS_MASK (0xFFFFFF3F)
179 #define FBCS_CSCR_BEM (0x00000020)
180 #define FBCS_CSCR_BSTR (0x00000010)
181 #define FBCS_CSCR_BSTW (0x00000008)
183 #define FBCS_CSCR_PS_16 (0x00000080)
184 #define FBCS_CSCR_PS_8 (0x00000040)
185 #define FBCS_CSCR_PS_32 (0x00000000)
188 #endif /* __FLEXBUS_H */