git.sur5r.net Git - u-boot/blob - arch/m68k/include/asm/coldfire/qspi.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Queue Serial Peripheral Interface Memory Map
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 #ifndef __QSPI_H__
  10 #define __QSPI_H__
  11
  12 /* QSPI module registers */
  13 typedef struct qspi_ctrl {
  14         u16 mr;                 /* 0x00 Mode */
  15         u16 res1;
  16         u16 dlyr;               /* 0x04 Delay */
  17         u16 res2;
  18         u16 wr;                 /* 0x08 Wrap */
  19         u16 res3;
  20         u16 ir;                 /* 0x0C Interrupt */
  21         u16 res4;
  22         u16 ar;                 /* 0x10 Address */
  23         u16 res5;
  24         u16 dr;                 /* 0x14 Data */
  25         u16 res6;
  26 } qspi_t;
  27
  28 /* MR */
  29 #define QSPI_QMR_MSTR                   (0x8000)
  30 #define QSPI_QMR_DOHIE                  (0x4000)
  31 #define QSPI_QMR_BITS(x)                (((x)&0x000F)<<10)
  32 #define QSPI_QMR_BITS_MASK              (0xC3FF)
  33 #define QSPI_QMR_BITS_8                 (0x2000)
  34 #define QSPI_QMR_BITS_9                 (0x2400)
  35 #define QSPI_QMR_BITS_10                (0x2800)
  36 #define QSPI_QMR_BITS_11                (0x2C00)
  37 #define QSPI_QMR_BITS_12                (0x3000)
  38 #define QSPI_QMR_BITS_13                (0x3400)
  39 #define QSPI_QMR_BITS_14                (0x3800)
  40 #define QSPI_QMR_BITS_15                (0x3C00)
  41 #define QSPI_QMR_BITS_16                (0x0000)
  42 #define QSPI_QMR_CPOL                   (0x0200)
  43 #define QSPI_QMR_CPHA                   (0x0100)
  44 #define QSPI_QMR_BAUD(x)                ((x)&0x00FF)
  45 #define QSPI_QMR_BAUD_MASK              (0xFF00)
  46
  47 /* DLYR */
  48 #define QSPI_QDLYR_SPE                  (0x8000)
  49 #define QSPI_QDLYR_QCD(x)               (((x)&0x007F)<<8)
  50 #define QSPI_QDLYR_QCD_MASK             (0x80FF)
  51 #define QSPI_QDLYR_DTL(x)               ((x)&0x00FF)
  52 #define QSPI_QDLYR_DTL_MASK             (0xFF00)
  53
  54 /* WR */
  55 #define QSPI_QWR_HALT                   (0x8000)
  56 #define QSPI_QWR_WREN                   (0x4000)
  57 #define QSPI_QWR_WRTO                   (0x2000)
  58 #define QSPI_QWR_CSIV                   (0x1000)
  59 #define QSPI_QWR_ENDQP(x)               (((x)&0x000F)<<8)
  60 #define QSPI_QWR_ENDQP_MASK             (0xF0FF)
  61 #define QSPI_QWR_CPTQP(x)               (((x)&0x000F)<<4)
  62 #define QSPI_QWR_CPTQP_MASK             (0xFF0F)
  63 #define QSPI_QWR_NEWQP(x)               ((x)&0x000F)
  64 #define QSPI_QWR_NEWQP_MASK             (0xFFF0)
  65
  66 /* IR */
  67 #define QSPI_QIR_WCEFB                  (0x8000)
  68 #define QSPI_QIR_ABRTB                  (0x4000)
  69 #define QSPI_QIR_ABRTL                  (0x1000)
  70 #define QSPI_QIR_WCEFE                  (0x0800)
  71 #define QSPI_QIR_ABRTE                  (0x0400)
  72 #define QSPI_QIR_SPIFE                  (0x0100)
  73 #define QSPI_QIR_WCEF                   (0x0008)
  74 #define QSPI_QIR_ABRT                   (0x0004)
  75 #define QSPI_QIR_SPIF                   (0x0001)
  76
  77 /* AR */
  78 #define QSPI_QAR_ADDR(x)                ((x)&0x003F)
  79 #define QSPI_QAR_ADDR_MASK              (0xFFC0)
  80 #define QSPI_QAR_TRANS                  (0x0000)
  81 #define QSPI_QAR_RECV                   (0x0010)
  82 #define QSPI_QAR_CMD                    (0x0020)
  83
  84 /* DR with RAM command word definitions */
  85 #define QSPI_QDR_CONT                   (0x8000)
  86 #define QSPI_QDR_BITSE                  (0x4000)
  87 #define QSPI_QDR_DT                     (0x2000)
  88 #define QSPI_QDR_DSCK                   (0x1000)
  89 #define QSPI_QDR_QSPI_CS3               (0x0800)
  90 #define QSPI_QDR_QSPI_CS2               (0x0400)
  91 #define QSPI_QDR_QSPI_CS1               (0x0200)
  92 #define QSPI_QDR_QSPI_CS0               (0x0100)
  93
  94 #endif                          /* __QSPI_H__ */