1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * fec.h -- Fast Ethernet Controller definitions
5 * Some definitions copied from commproc.h for MPC8xx:
6 * MPC8xx Communication Processor Module.
7 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
9 * Add FEC Structure and definitions
10 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
11 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
19 /* Buffer descriptors used FEC.
21 typedef struct cpm_buf_desc {
22 ushort cbd_sc; /* Status and Control */
23 ushort cbd_datlen; /* Data length in buffer */
24 uint cbd_bufaddr; /* Buffer address in host memory */
27 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
28 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
29 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
30 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
31 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
32 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
33 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
34 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
35 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
36 #define BD_SC_BR ((ushort)0x0020) /* Break received */
37 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
38 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
39 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
40 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
42 /* Buffer descriptor control/status used by Ethernet receive.
44 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
45 #define BD_ENET_RX_RO1 ((ushort)0x4000)
46 #define BD_ENET_RX_WRAP ((ushort)0x2000)
47 #define BD_ENET_RX_INTR ((ushort)0x1000)
48 #define BD_ENET_RX_RO2 BD_ENET_RX_INTR
49 #define BD_ENET_RX_LAST ((ushort)0x0800)
50 #define BD_ENET_RX_FIRST ((ushort)0x0400)
51 #define BD_ENET_RX_MISS ((ushort)0x0100)
52 #define BD_ENET_RX_BC ((ushort)0x0080)
53 #define BD_ENET_RX_MC ((ushort)0x0040)
54 #define BD_ENET_RX_LG ((ushort)0x0020)
55 #define BD_ENET_RX_NO ((ushort)0x0010)
56 #define BD_ENET_RX_SH ((ushort)0x0008)
57 #define BD_ENET_RX_CR ((ushort)0x0004)
58 #define BD_ENET_RX_OV ((ushort)0x0002)
59 #define BD_ENET_RX_CL ((ushort)0x0001)
60 #define BD_ENET_RX_TR BD_ENET_RX_CL
61 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
63 /* Buffer descriptor control/status used by Ethernet transmit.
65 #define BD_ENET_TX_READY ((ushort)0x8000)
66 #define BD_ENET_TX_PAD ((ushort)0x4000)
67 #define BD_ENET_TX_TO1 BD_ENET_TX_PAD
68 #define BD_ENET_TX_WRAP ((ushort)0x2000)
69 #define BD_ENET_TX_INTR ((ushort)0x1000)
70 #define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
71 #define BD_ENET_TX_LAST ((ushort)0x0800)
72 #define BD_ENET_TX_TC ((ushort)0x0400)
73 #define BD_ENET_TX_DEF ((ushort)0x0200)
74 #define BD_ENET_TX_ABC BD_ENET_TX_DEF
75 #define BD_ENET_TX_HB ((ushort)0x0100)
76 #define BD_ENET_TX_LC ((ushort)0x0080)
77 #define BD_ENET_TX_RL ((ushort)0x0040)
78 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
79 #define BD_ENET_TX_UN ((ushort)0x0002)
80 #define BD_ENET_TX_CSL ((ushort)0x0001)
81 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
83 /*********************************************************************
84 * Fast Ethernet Controller (FEC)
85 *********************************************************************/
86 /* FEC private information */
96 cbd_t *rxbd; /* Rx BD */
97 cbd_t *txbd; /* Tx BD */
102 struct fec_info_s *next;
106 /* Register read/write struct */
115 u8 resv1[0x28]; /* 0x18 */
118 u8 resv2[0x44]; /* 0x48 */
121 u8 resv3[0x10]; /* 0x94 */
125 u8 resv4[0x50]; /* 0xB0 */
126 u32 opd; /* 0x100 - dummy */
128 u32 mibc; /* 0x108 */
129 u8 resv5[0x38]; /* 0x10C */
131 u8 resv6[0x270]; /* 0x148 */
132 u32 iaur; /* 0x3B8 - dummy */
133 u32 ialr; /* 0x3BC - dummy */
134 u32 palr; /* 0x3C0 */
135 u32 paur; /* 0x3C4 */
136 u32 gaur; /* 0x3C8 */
137 u32 galr; /* 0x3CC */
138 u32 erdsr; /* 0x3D0 */
139 u32 etdsr; /* 0x3D4 */
140 u32 emrbr; /* 0x3D8 */
141 u8 resv12[0x74]; /* 0x18C */
185 u32 rmon_t_crc_align;
186 u32 rmon_t_undersize;
193 u32 rmon_t_p128to255;
194 u32 rmon_t_p256to511;
195 u32 rmon_t_p512to1023;
196 u32 rmon_t_p1024to2047;
197 u32 rmon_t_p_gte2048;
211 u32 ieee_t_octets_ok;
218 u32 rmon_r_crc_align;
219 u32 rmon_r_undersize;
226 u32 rmon_r_p128to255;
227 u32 rmon_r_p256to511;
228 u32 rmon_r_p512to1023;
229 u32 rmon_r_p1024to2047;
230 u32 rmon_r_p_gte2048;
239 u32 ieee_r_octets_ok;
241 #endif /* CONFIG_MCFFEC */
243 /*********************************************************************
244 * Fast Ethernet Controller (FEC)
245 *********************************************************************/
246 /* Bit definitions and macros for FEC_EIR */
247 #define FEC_EIR_CLEAR_ALL (0xFFF80000)
248 #define FEC_EIR_HBERR (0x80000000)
249 #define FEC_EIR_BABR (0x40000000)
250 #define FEC_EIR_BABT (0x20000000)
251 #define FEC_EIR_GRA (0x10000000)
252 #define FEC_EIR_TXF (0x08000000)
253 #define FEC_EIR_TXB (0x04000000)
254 #define FEC_EIR_RXF (0x02000000)
255 #define FEC_EIR_RXB (0x01000000)
256 #define FEC_EIR_MII (0x00800000)
257 #define FEC_EIR_EBERR (0x00400000)
258 #define FEC_EIR_LC (0x00200000)
259 #define FEC_EIR_RL (0x00100000)
260 #define FEC_EIR_UN (0x00080000)
262 /* Bit definitions and macros for FEC_RDAR */
263 #define FEC_RDAR_R_DES_ACTIVE (0x01000000)
265 /* Bit definitions and macros for FEC_TDAR */
266 #define FEC_TDAR_X_DES_ACTIVE (0x01000000)
268 /* Bit definitions and macros for FEC_ECR */
269 #define FEC_ECR_ETHER_EN (0x00000002)
270 #define FEC_ECR_RESET (0x00000001)
272 /* Bit definitions and macros for FEC_MMFR */
273 #define FEC_MMFR_DATA(x) (((x)&0xFFFF))
274 #define FEC_MMFR_ST(x) (((x)&0x03)<<30)
275 #define FEC_MMFR_ST_01 (0x40000000)
276 #define FEC_MMFR_OP_RD (0x20000000)
277 #define FEC_MMFR_OP_WR (0x10000000)
278 #define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
279 #define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
280 #define FEC_MMFR_TA(x) (((x)&0x03)<<16)
281 #define FEC_MMFR_TA_10 (0x00020000)
283 /* Bit definitions and macros for FEC_MSCR */
284 #define FEC_MSCR_DIS_PREAMBLE (0x00000080)
285 #define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
287 /* Bit definitions and macros for FEC_MIBC */
288 #define FEC_MIBC_MIB_DISABLE (0x80000000)
289 #define FEC_MIBC_MIB_IDLE (0x40000000)
291 /* Bit definitions and macros for FEC_RCR */
292 #define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
293 #define FEC_RCR_FCE (0x00000020)
294 #define FEC_RCR_BC_REJ (0x00000010)
295 #define FEC_RCR_PROM (0x00000008)
296 #define FEC_RCR_MII_MODE (0x00000004)
297 #define FEC_RCR_DRT (0x00000002)
298 #define FEC_RCR_LOOP (0x00000001)
300 /* Bit definitions and macros for FEC_TCR */
301 #define FEC_TCR_RFC_PAUSE (0x00000010)
302 #define FEC_TCR_TFC_PAUSE (0x00000008)
303 #define FEC_TCR_FDEN (0x00000004)
304 #define FEC_TCR_HBC (0x00000002)
305 #define FEC_TCR_GTS (0x00000001)
307 /* Bit definitions and macros for FEC_PAUR */
308 #define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
309 #define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
311 /* Bit definitions and macros for FEC_OPD */
312 #define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
313 #define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
315 /* Bit definitions and macros for FEC_TFWR */
316 #define FEC_TFWR_X_WMRK(x) ((x)&0x03)
317 #define FEC_TFWR_X_WMRK_64 (0x01)
318 #define FEC_TFWR_X_WMRK_128 (0x02)
319 #define FEC_TFWR_X_WMRK_192 (0x03)
321 /* Bit definitions and macros for FEC_FRBR */
322 #define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
324 /* Bit definitions and macros for FEC_FRSR */
325 #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
327 /* Bit definitions and macros for FEC_ERDSR */
328 #define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
330 /* Bit definitions and macros for FEC_ETDSR */
331 #define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
333 /* Bit definitions and macros for FEC_EMRBR */
334 #define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
336 #define FEC_RESET_DELAY 100
337 #define FEC_RX_TOUT 100
339 int fecpin_setclear(struct eth_device *dev, int setclear);
341 #ifdef CONFIG_SYS_DISCOVER_PHY
342 void __mii_init(void);
343 uint mii_send(uint mii_cmd);
344 int mii_discover_phy(struct eth_device *dev);
345 int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
346 int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,