2 * ColdFire Internal Memory Map and Defines
4 * Copyright 2004-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
13 #if defined(CONFIG_MCF520x)
14 #include <asm/immap_520x.h>
15 #include <asm/m520x.h>
17 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
18 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
22 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
23 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
24 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
25 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
26 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
27 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
28 #define CONFIG_SYS_TMRINTR_PRI (6)
29 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
33 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
34 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
35 #define CONFIG_SYS_PIT_PRESCALE (6)
38 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
39 #define CONFIG_SYS_NUM_IRQS (128)
40 #endif /* CONFIG_M520x */
43 #include <asm/immap_5227x.h>
44 #include <asm/m5227x.h>
46 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
48 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
51 #define CONFIG_SYS_LCD_BASE (MMAP_LCD)
56 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
57 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
58 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
59 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
60 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
61 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
62 #define CONFIG_SYS_TMRINTR_PRI (6)
63 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
67 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
68 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
69 #define CONFIG_SYS_PIT_PRESCALE (6)
72 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
73 #define CONFIG_SYS_NUM_IRQS (128)
74 #endif /* CONFIG_M52277 */
77 #include <asm/immap_5235.h>
78 #include <asm/m5235.h>
80 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
81 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
85 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
86 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
87 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
88 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
89 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
90 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
91 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
92 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
96 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
97 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
98 #define CONFIG_SYS_PIT_PRESCALE (6)
101 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
102 #define CONFIG_SYS_NUM_IRQS (128)
103 #endif /* CONFIG_M5235 */
106 #include <asm/immap_5249.h>
107 #include <asm/m5249.h>
109 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
111 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
112 #define CONFIG_SYS_NUM_IRQS (64)
116 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
117 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
118 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
119 #define CONFIG_SYS_TMRINTR_NO (31)
120 #define CONFIG_SYS_TMRINTR_MASK (0x00000400)
121 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
122 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
123 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
125 #endif /* CONFIG_M5249 */
128 #include <asm/immap_5253.h>
129 #include <asm/m5249.h>
130 #include <asm/m5253.h>
132 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
134 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
135 #define CONFIG_SYS_NUM_IRQS (64)
139 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
140 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
141 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
142 #define CONFIG_SYS_TMRINTR_NO (27)
143 #define CONFIG_SYS_TMRINTR_MASK (0x00000400)
144 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
145 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
146 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
148 #endif /* CONFIG_M5253 */
151 #include <asm/immap_5271.h>
152 #include <asm/m5271.h>
154 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
155 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
159 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
160 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
161 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
162 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
163 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
164 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
165 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
166 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
169 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
170 #define CONFIG_SYS_NUM_IRQS (128)
171 #endif /* CONFIG_M5271 */
174 #include <asm/immap_5272.h>
175 #include <asm/m5272.h>
177 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
178 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
180 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
181 #define CONFIG_SYS_NUM_IRQS (64)
185 #define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
186 #define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
187 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
188 #define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
189 #define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
190 #define CONFIG_SYS_TMRINTR_PEND (0)
191 #define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
192 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
194 #endif /* CONFIG_M5272 */
197 #include <asm/immap_5275.h>
198 #include <asm/m5275.h>
200 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
201 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
202 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
204 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
205 #define CONFIG_SYS_NUM_IRQS (192)
209 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
210 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
211 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
212 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
213 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
214 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
215 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
216 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
218 #endif /* CONFIG_M5275 */
221 #include <asm/immap_5282.h>
222 #include <asm/m5282.h>
224 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
225 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
227 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
228 #define CONFIG_SYS_NUM_IRQS (128)
232 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
233 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
234 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
235 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
236 #define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
237 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
238 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
239 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
241 #endif /* CONFIG_M5282 */
243 #if defined(CONFIG_MCF5301x)
244 #include <asm/immap_5301x.h>
245 #include <asm/m5301x.h>
247 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
248 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
249 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
251 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
255 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
256 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
257 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
258 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
259 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
260 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
261 #define CONFIG_SYS_TMRINTR_PRI (6)
262 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
266 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
267 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
268 #define CONFIG_SYS_PIT_PRESCALE (6)
271 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
272 #define CONFIG_SYS_NUM_IRQS (128)
273 #endif /* CONFIG_M5301x */
275 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
276 #include <asm/immap_5329.h>
277 #include <asm/m5329.h>
279 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
280 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
281 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
285 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
286 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
287 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
288 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
289 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
290 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
291 #define CONFIG_SYS_TMRINTR_PRI (6)
292 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
296 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
297 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
298 #define CONFIG_SYS_PIT_PRESCALE (6)
301 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
302 #define CONFIG_SYS_NUM_IRQS (128)
303 #endif /* CONFIG_M5329 && CONFIG_M5373 */
305 #if defined(CONFIG_M54418)
306 #include <asm/immap_5441x.h>
307 #include <asm/m5441x.h>
309 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
310 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
312 #if (CONFIG_SYS_UART_PORT < 4)
313 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
314 (CONFIG_SYS_UART_PORT * 0x4000))
316 #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
317 ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
320 #define MMAP_DSPI MMAP_DSPI0
321 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
325 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
326 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
327 #define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
328 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
329 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
330 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
331 #define CONFIG_SYS_TMRINTR_PRI (6)
332 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
336 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
337 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
338 #define CONFIG_SYS_PIT_PRESCALE (6)
341 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
342 #define CONFIG_SYS_NUM_IRQS (128)
344 #endif /* CONFIG_M54418 */
346 #if defined(CONFIG_M54451) || defined(CONFIG_M54455)
347 #include <asm/immap_5445x.h>
348 #include <asm/m5445x.h>
350 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
351 #if defined(CONFIG_M54455EVB)
352 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
355 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
357 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
361 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
362 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
363 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
364 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
365 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
366 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
367 #define CONFIG_SYS_TMRINTR_PRI (6)
368 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
372 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
373 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
374 #define CONFIG_SYS_PIT_PRESCALE (6)
377 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
378 #define CONFIG_SYS_NUM_IRQS (128)
381 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
382 #define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
383 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
384 #define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
386 #endif /* CONFIG_M54451 || CONFIG_M54455 */
389 #include <asm/immap_547x_8x.h>
390 #include <asm/m547x_8x.h>
392 #ifdef CONFIG_FSLDMAFEC
393 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
394 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
396 #define FEC0_RX_TASK 0
397 #define FEC0_TX_TASK 1
398 #define FEC0_RX_PRIORITY 6
399 #define FEC0_TX_PRIORITY 7
400 #define FEC0_RX_INIT 16
401 #define FEC0_TX_INIT 17
402 #define FEC1_RX_TASK 2
403 #define FEC1_TX_TASK 3
404 #define FEC1_RX_PRIORITY 6
405 #define FEC1_TX_PRIORITY 7
406 #define FEC1_RX_INIT 30
407 #define FEC1_TX_INIT 31
410 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
413 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
414 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
415 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
416 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
417 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
418 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
419 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
420 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
423 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
424 #define CONFIG_SYS_NUM_IRQS (128)
427 #define CONFIG_SYS_PCI_BAR0 (0x40000000)
428 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
429 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
430 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
432 #endif /* CONFIG_M547x */
435 #include <asm/immap_547x_8x.h>
436 #include <asm/m547x_8x.h>
438 #ifdef CONFIG_FSLDMAFEC
439 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
440 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
442 #define FEC0_RX_TASK 0
443 #define FEC0_TX_TASK 1
444 #define FEC0_RX_PRIORITY 6
445 #define FEC0_TX_PRIORITY 7
446 #define FEC0_RX_INIT 16
447 #define FEC0_TX_INIT 17
448 #define FEC1_RX_TASK 2
449 #define FEC1_TX_TASK 3
450 #define FEC1_RX_PRIORITY 6
451 #define FEC1_TX_PRIORITY 7
452 #define FEC1_RX_INIT 30
453 #define FEC1_TX_INIT 31
456 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
460 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
461 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
462 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
463 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
464 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
465 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
466 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
467 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
470 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
471 #define CONFIG_SYS_NUM_IRQS (128)
474 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
475 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
476 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
477 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
479 #endif /* CONFIG_M548x */
481 #endif /* __IMMAP_H */