2 * MCF5275 Internal Memory Map
4 * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
5 * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
7 * SPDX-License-Identifier: GPL-2.0+
14 * Define the 5275 SIM register set addresses. These are similar,
15 * but not quite identical to the 5282 registers and offsets.
17 #define MCF_GPIO_PAR_UART 0x10007c
18 #define UART0_ENABLE_MASK 0x000f
19 #define UART1_ENABLE_MASK 0x00f0
20 #define UART2_ENABLE_MASK 0x3f00
22 #define MCF_GPIO_PAR_FECI2C 0x100082
23 #define PAR_SDA_ENABLE_MASK 0x0003
24 #define PAR_SCL_ENABLE_MASK 0x000c
26 #define MCFSIM_WRRR 0x140000
27 #define MCFSIM_SDCR 0x40
29 /*********************************************************************
30 * SDRAM Controller (SDRAMC)
31 *********************************************************************/
33 /* Register read/write macros */
34 #define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
35 #define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
36 #define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
37 #define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
38 #define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
39 #define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
40 #define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
41 #define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
43 /* Bit definitions and macros for MCF_SDRAMC_SDMR */
44 #define MCF_SDRAMC_SDMR_CMD (0x00010000)
45 #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
46 #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
47 #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
48 #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
50 /* Bit definitions and macros for MCF_SDRAMC_SDCR */
51 #define MCF_SDRAMC_SDCR_IPALL (0x00000002)
52 #define MCF_SDRAMC_SDCR_IREF (0x00000004)
53 #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10)
54 #define MCF_SDRAMC_SDCR_DQP_BP (0x00008000)
55 #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
56 #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
57 #define MCF_SDRAMC_SDCR_REF (0x10000000)
58 #define MCF_SDRAMC_SDCR_CKE (0x40000000)
59 #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
61 /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
62 #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
63 #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
64 #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
65 #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
66 #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
67 #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
68 #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
70 /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
71 #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
72 #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
73 #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
74 #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
76 /* Bit definitions and macros for MCF_SDRAMC_SDBARn */
77 #define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18)
78 #define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000)
80 /* Bit definitions and macros for MCF_SDRAMC_SDMRn */
81 #define MCF_SDRAMC_SDMRn_V (0x00000001)
82 #define MCF_SDRAMC_SDMRn_WP (0x00000080)
83 #define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18)
84 #define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000)
85 #define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000)
86 #define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000)
87 #define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000)
88 #define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000)
89 #define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000)
90 #define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000)
91 #define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000)
92 #define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000)
93 #define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000)
94 #define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000)
95 #define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000)
96 #define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000)
97 #define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000)
98 #define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000)
99 #define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000)
100 #define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000)
101 #define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000)
102 #define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000)
104 /*********************************************************************
105 * Interrupt Controller (INTC)
106 ********************************************************************/
107 #define INT0_LO_RSVD0 (0)
108 #define INT0_LO_EPORT1 (1)
109 #define INT0_LO_EPORT2 (2)
110 #define INT0_LO_EPORT3 (3)
111 #define INT0_LO_EPORT4 (4)
112 #define INT0_LO_EPORT5 (5)
113 #define INT0_LO_EPORT6 (6)
114 #define INT0_LO_EPORT7 (7)
115 #define INT0_LO_SCM (8)
116 #define INT0_LO_DMA0 (9)
117 #define INT0_LO_DMA1 (10)
118 #define INT0_LO_DMA2 (11)
119 #define INT0_LO_DMA3 (12)
120 #define INT0_LO_UART0 (13)
121 #define INT0_LO_UART1 (14)
122 #define INT0_LO_UART2 (15)
123 #define INT0_LO_RSVD1 (16)
124 #define INT0_LO_I2C (17)
125 #define INT0_LO_QSPI (18)
126 #define INT0_LO_DTMR0 (19)
127 #define INT0_LO_DTMR1 (20)
128 #define INT0_LO_DTMR2 (21)
129 #define INT0_LO_DTMR3 (22)
130 #define INT0_LO_FEC0_TXF (23)
131 #define INT0_LO_FEC0_TXB (24)
132 #define INT0_LO_FEC0_UN (25)
133 #define INT0_LO_FEC0_RL (26)
134 #define INT0_LO_FEC0_RXF (27)
135 #define INT0_LO_FEC0_RXB (28)
136 #define INT0_LO_FEC0_MII (29)
137 #define INT0_LO_FEC0_LC (30)
138 #define INT0_LO_FEC0_HBERR (31)
139 #define INT0_HI_FEC0_GRA (32)
140 #define INT0_HI_FEC0_EBERR (33)
141 #define INT0_HI_FEC0_BABT (34)
142 #define INT0_HI_FEC0_BABR (35)
143 #define INT0_HI_PIT0 (36)
144 #define INT0_HI_PIT1 (37)
145 #define INT0_HI_PIT2 (38)
146 #define INT0_HI_PIT3 (39)
147 #define INT0_HI_RNG (40)
148 #define INT0_HI_SKHA (41)
149 #define INT0_HI_MDHA (42)
150 #define INT0_HI_USB (43)
151 #define INT0_HI_USB_EP0 (44)
152 #define INT0_HI_USB_EP1 (45)
153 #define INT0_HI_USB_EP2 (46)
154 #define INT0_HI_USB_EP3 (47)
158 #define INT1_LO_FEC1_TXF (23)
159 #define INT1_LO_FEC1_TXB (24)
160 #define INT1_LO_FEC1_UN (25)
161 #define INT1_LO_FEC1_RL (26)
162 #define INT1_LO_FEC1_RXF (27)
163 #define INT1_LO_FEC1_RXB (28)
164 #define INT1_LO_FEC1_MII (29)
165 #define INT1_LO_FEC1_LC (30)
166 #define INT1_LO_FEC1_HBERR (31)
167 #define INT1_HI_FEC1_GRA (32)
168 #define INT1_HI_FEC1_EBERR (33)
169 #define INT1_HI_FEC1_BABT (34)
170 #define INT1_HI_FEC1_BABR (35)
173 /* Bit definitions and macros for RCR */
174 #define RCM_RCR_FRCRSTOUT (0x40)
175 #define RCM_RCR_SOFTRST (0x80)
177 #define FMPLL_SYNSR_LOCK (0x00000008)
179 #endif /* __M5275_H__ */