2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __MICROBLAZE_CACHE_H__
8 #define __MICROBLAZE_CACHE_H__
11 * The microblaze can have either a 4 or 16 byte cacheline depending on whether
12 * you are using OPB(4) or CacheLink(16). If the board config has not specified
13 * a cacheline size we assume the larger value of 16 bytes for DMA buffer
16 #ifdef CONFIG_SYS_CACHELINE_SIZE
17 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
19 #define ARCH_DMA_MINALIGN 16
22 #endif /* __MICROBLAZE_CACHE_H__ */