4 * Hardcoded to UART 0 for now
5 * Speed and options also hardcoded to 115200 8N1
7 * Copyright (c) 2003 Thomas.Lange@corelatus.se
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/au1x00.h>
32 #include <linux/compiler.h>
34 /******************************************************************************
36 * serial_init - initialize a channel
38 * This routine initializes the number of data bits, parity
39 * and set the selected baud rate. Interrupts are disabled.
40 * Set the modem control signals if the option is selected.
45 static int au1x00_serial_init(void)
47 volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
48 volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
50 /* Enable clocks first */
51 *uart_enable = UART_EN_CE;
53 /* Then release reset */
54 /* Must release reset before setting other regs */
55 *uart_enable = UART_EN_CE|UART_EN_E;
57 /* Activate fifos, reset tx and rx */
58 /* Set tx trigger level to 12 */
59 *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
60 UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
68 static void au1x00_serial_setbrg(void)
70 volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
71 volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
72 volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
76 /* sd is system clock divisor */
77 /* see section 10.4.5 in au1550 datasheet */
78 sd = (*sys_powerctrl & 0x03) + 2;
80 /* calulate 2x baudrate and round */
81 divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
84 divisorx2 = divisorx2 + 1;
86 *uart_clk = divisorx2 / 2;
88 /* Set parity, stop bits and word length to 8N1 */
89 *uart_lcr = UART_LCR_WLEN8;
92 static void au1x00_serial_putc(const char c)
94 volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
95 volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
98 au1x00_serial_putc('\r');
100 /* Wait for fifo to shift out some bytes */
101 while((*uart_lsr&UART_LSR_THRE)==0);
106 static void au1x00_serial_puts(const char *s)
112 static int au1x00_serial_getc(void)
114 volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
117 while (!serial_tstc());
123 static int au1x00_serial_tstc(void)
125 volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
127 if(*uart_lsr&UART_LSR_DR){
134 #ifdef CONFIG_SERIAL_MULTI
135 static struct serial_device au1x00_serial_drv = {
136 .name = "au1x00_serial",
137 .start = au1x00_serial_init,
139 .setbrg = au1x00_serial_setbrg,
140 .putc = au1x00_serial_putc,
141 .puts = au1x00_serial_puts,
142 .getc = au1x00_serial_getc,
143 .tstc = au1x00_serial_tstc,
146 void au1x00_serial_initialize(void)
148 serial_register(&au1x00_serial_drv);
151 __weak struct serial_device *default_serial_console(void)
153 return &au1x00_serial_drv;
156 int serial_init(void)
158 return au1x00_serial_init();
161 void serial_setbrg(void)
163 au1x00_serial_setbrg();
166 void serial_putc(const char c)
168 au1x00_serial_putc(c);
171 void serial_puts(const char *s)
173 au1x00_serial_puts(s);
176 int serial_getc(void)
178 return au1x00_serial_getc();
181 int serial_tstc(void)
183 return au1x00_serial_tstc();