2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
14 #include <asm/addrspace.h>
15 #include <asm/cacheops.h>
17 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
18 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
24 * 16kB is the maximum size of instruction and data caches on MIPS 4K,
25 * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
27 * Note that the above size is the maximum size of primary cache. U-Boot
28 * doesn't have L2 cache support for now.
30 #define MIPS_MAX_CACHE_SIZE 0x10000
32 #define INDEX_BASE CKSEG0
34 .macro cache_op op addr
42 .macro f_fill64 dst, offset, val
43 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
44 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
45 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
46 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
47 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
48 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
49 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
50 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
52 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
53 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
54 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
55 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
56 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
57 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
58 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
59 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
64 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
66 LEAF(mips_init_icache)
69 /* clear tag to invalidate */
72 1: cache_op INDEX_STORE_TAG_I t0
75 /* fill once, so data field parity is correct */
80 /* invalidate again - prudent but not strictly neccessary */
82 1: cache_op INDEX_STORE_TAG_I t0
89 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
91 LEAF(mips_init_dcache)
97 1: cache_op INDEX_STORE_TAG_D t0
100 /* load from each line (in cached space) */
101 PTR_LI t0, INDEX_BASE
102 2: LONG_L zero, 0(t0)
106 PTR_LI t0, INDEX_BASE
107 1: cache_op INDEX_STORE_TAG_D t0
111 END(mips_init_dcache)
114 * mips_cache_reset - low level initialisation of the primary caches
116 * This routine initialises the primary caches to ensure that they have good
117 * parity. It must be called by the ROM before any cached locations are used
118 * to prevent the possibility of data with bad parity being written to memory.
120 * To initialise the instruction cache it is essential that a source of data
121 * with good parity is available. This routine will initialise an area of
122 * memory starting at location zero to be used as a source of parity.
127 NESTED(mips_cache_reset, 0, ra)
129 li t2, CONFIG_SYS_ICACHE_SIZE
130 li t3, CONFIG_SYS_DCACHE_SIZE
131 li t8, CONFIG_SYS_CACHELINE_SIZE
133 li v0, MIPS_MAX_CACHE_SIZE
136 * Now clear that much memory starting from zero.
141 f_fill64 a0, -64, zero
145 * The caches are probably in an indeterminate state,
146 * so we force good parity into them by doing an
147 * invalidate, load/fill, invalidate for each line.
151 * Assume bottom of RAM will generate good parity for the cache.
155 * Initialize the I-cache first,
159 PTR_LA v1, mips_init_icache
163 * then initialize D-cache.
167 PTR_LA v1, mips_init_dcache
171 END(mips_cache_reset)
174 * dcache_status - get cache status
176 * RETURNS: 0 - cache disabled; 1 - cache enabled
181 li t1, CONF_CM_UNCACHED
182 andi t0, t0, CONF_CM_CMASK
190 * dcache_disable - disable cache
199 ori t0, t0, CONF_CM_UNCACHED
205 * dcache_enable - enable cache
212 ori t0, CONF_CM_CMASK
213 xori t0, CONF_CM_CMASK
214 ori t0, CONFIG_SYS_MIPS_CACHE_MODE