2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
14 #include <asm/addrspace.h>
15 #include <asm/cacheops.h>
17 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
18 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
23 #define INDEX_BASE CKSEG0
25 .macro cache_op op addr
33 .macro f_fill64 dst, offset, val
34 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
35 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
36 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
37 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
38 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
39 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
40 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
41 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
43 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
44 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
45 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
46 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
47 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
48 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
49 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
50 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
55 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
57 LEAF(mips_init_icache)
60 /* clear tag to invalidate */
63 1: cache_op INDEX_STORE_TAG_I t0
66 /* fill once, so data field parity is correct */
71 /* invalidate again - prudent but not strictly neccessary */
73 1: cache_op INDEX_STORE_TAG_I t0
80 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
82 LEAF(mips_init_dcache)
88 1: cache_op INDEX_STORE_TAG_D t0
91 /* load from each line (in cached space) */
98 1: cache_op INDEX_STORE_TAG_D t0
102 END(mips_init_dcache)
105 * mips_cache_reset - low level initialisation of the primary caches
107 * This routine initialises the primary caches to ensure that they have good
108 * parity. It must be called by the ROM before any cached locations are used
109 * to prevent the possibility of data with bad parity being written to memory.
111 * To initialise the instruction cache it is essential that a source of data
112 * with good parity is available. This routine will initialise an area of
113 * memory starting at location zero to be used as a source of parity.
118 NESTED(mips_cache_reset, 0, ra)
121 #if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
122 !defined(CONFIG_SYS_CACHELINE_SIZE)
123 /* read Config1 for use below */
124 mfc0 t5, CP0_CONFIG, 1
127 #ifdef CONFIG_SYS_CACHELINE_SIZE
128 li t7, CONFIG_SYS_CACHELINE_SIZE
129 li t8, CONFIG_SYS_CACHELINE_SIZE
131 /* Detect I-cache line size. */
132 srl t8, t5, MIPS_CONF1_IL_SHIFT
133 andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
138 1: /* Detect D-cache line size. */
139 srl t7, t5, MIPS_CONF1_DL_SHIFT
140 andi t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
147 #ifdef CONFIG_SYS_ICACHE_SIZE
148 li t2, CONFIG_SYS_ICACHE_SIZE
150 /* Detect I-cache size. */
151 srl t6, t5, MIPS_CONF1_IS_SHIFT
152 andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
158 1: /* At this point t4 == I-cache sets. */
160 srl t6, t5, MIPS_CONF1_IA_SHIFT
161 andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
163 /* At this point t6 == I-cache ways. */
167 #ifdef CONFIG_SYS_DCACHE_SIZE
168 li t3, CONFIG_SYS_DCACHE_SIZE
170 /* Detect D-cache size. */
171 srl t6, t5, MIPS_CONF1_DS_SHIFT
172 andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
178 1: /* At this point t4 == I-cache sets. */
180 srl t6, t5, MIPS_CONF1_DA_SHIFT
181 andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
183 /* At this point t6 == I-cache ways. */
187 /* Determine the largest L1 cache size */
188 #if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
189 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
190 li v0, CONFIG_SYS_ICACHE_SIZE
192 li v0, CONFIG_SYS_DCACHE_SIZE
200 * Now clear that much memory starting from zero.
205 f_fill64 a0, -64, zero
209 * The caches are probably in an indeterminate state,
210 * so we force good parity into them by doing an
211 * invalidate, load/fill, invalidate for each line.
215 * Assume bottom of RAM will generate good parity for the cache.
219 * Initialize the I-cache first,
223 PTR_LA v1, mips_init_icache
227 * then initialize D-cache.
231 PTR_LA v1, mips_init_dcache
235 END(mips_cache_reset)
238 * dcache_status - get cache status
240 * RETURNS: 0 - cache disabled; 1 - cache enabled
245 li t1, CONF_CM_UNCACHED
246 andi t0, t0, CONF_CM_CMASK
254 * dcache_disable - disable cache
263 ori t0, t0, CONF_CM_UNCACHED
269 * dcache_enable - enable cache
276 ori t0, CONF_CM_CMASK
277 xori t0, CONF_CM_CMASK
278 ori t0, CONFIG_SYS_MIPS_CACHE_MODE