3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/mipsregs.h>
12 #include <asm/cacheops.h>
13 #include <asm/reboot.h>
15 #define cache_op(op,addr) \
16 __asm__ __volatile__( \
18 " .set noreorder \n" \
19 " .set mips3\n\t \n" \
23 : "i" (op), "R" (*(unsigned char *)(addr)))
25 void __attribute__((weak)) _machine_restart(void)
29 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
33 fprintf(stderr, "*** reset failed ***\n");
37 #ifdef CONFIG_SYS_CACHELINE_SIZE
39 static inline unsigned long icache_line_size(void)
41 return CONFIG_SYS_CACHELINE_SIZE;
44 static inline unsigned long dcache_line_size(void)
46 return CONFIG_SYS_CACHELINE_SIZE;
49 #else /* !CONFIG_SYS_CACHELINE_SIZE */
51 static inline unsigned long icache_line_size(void)
53 unsigned long conf1, il;
54 conf1 = read_c0_config1();
55 il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
61 static inline unsigned long dcache_line_size(void)
63 unsigned long conf1, dl;
64 conf1 = read_c0_config1();
65 dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
71 #endif /* !CONFIG_SYS_CACHELINE_SIZE */
73 void flush_cache(ulong start_addr, ulong size)
75 unsigned long ilsize = icache_line_size();
76 unsigned long dlsize = dcache_line_size();
77 unsigned long addr, aend;
79 /* aend will be miscalculated when size is zero, so we return here */
83 addr = start_addr & ~(dlsize - 1);
84 aend = (start_addr + size - 1) & ~(dlsize - 1);
86 if (ilsize == dlsize) {
87 /* flush I-cache & D-cache simultaneously */
89 cache_op(HIT_WRITEBACK_INV_D, addr);
90 cache_op(HIT_INVALIDATE_I, addr);
100 cache_op(HIT_WRITEBACK_INV_D, addr);
107 addr = start_addr & ~(ilsize - 1);
108 aend = (start_addr + size - 1) & ~(ilsize - 1);
110 cache_op(HIT_INVALIDATE_I, addr);
117 void flush_dcache_range(ulong start_addr, ulong stop)
119 unsigned long lsize = dcache_line_size();
120 unsigned long addr = start_addr & ~(lsize - 1);
121 unsigned long aend = (stop - 1) & ~(lsize - 1);
124 cache_op(HIT_WRITEBACK_INV_D, addr);
131 void invalidate_dcache_range(ulong start_addr, ulong stop)
133 unsigned long lsize = dcache_line_size();
134 unsigned long addr = start_addr & ~(lsize - 1);
135 unsigned long aend = (stop - 1) & ~(lsize - 1);
138 cache_op(HIT_INVALIDATE_D, addr);
145 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
147 write_c0_entrylo0(low0);
148 write_c0_pagemask(pagemask);
149 write_c0_entrylo1(low1);
150 write_c0_entryhi(hi);
151 write_c0_index(index);
155 int cpu_eth_init(bd_t *bis)
157 #ifdef CONFIG_SOC_AU1X00
158 au1x00_enet_initialize(bis);