2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
11 #include <asm/regdef.h>
12 #include <asm/mipsregs.h>
14 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
15 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
18 #ifndef CONFIG_SYS_INIT_SP_ADDR
19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
20 CONFIG_SYS_INIT_SP_OFFSET)
24 * For the moment disable interrupts, mark the kernel mode and
25 * set ST0_KX so that the CPU does not spit fire when using
28 .macro setup_c0_status set clr
31 or t0, ST0_CU0 | \set | 0x1f | \clr
44 /* U-boot entry point */
49 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
51 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
52 * access external NOR flashes. If the board boots from NOR flash the
53 * internal BootROM does a blind read at address 0xB0000010 to read the
54 * initial configuration for that EBU in order to access the flash
55 * device with correct parameters. This config option is board-specific.
57 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
59 #elif defined(CONFIG_MALTA)
61 * Linux expects the Board ID here.
63 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
68 /* TLB refill, 32 bit task */
73 /* XTLB refill, 64 bit task */
78 /* Cache error exception */
83 /* General exception */
88 /* Catch interrupt exceptions */
93 /* EJTAG debug exception */
100 /* Clear watch registers */
101 mtc0 zero, CP0_WATCHLO
102 mtc0 zero, CP0_WATCHHI
104 /* WP(Watch Pending), SW0/1 should be cleared */
111 mtc0 zero, CP0_COMPARE
113 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
114 /* CONFIG0 register */
115 li t0, CONF_CM_UNCACHED
126 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
127 /* Initialize any external memory */
132 /* Initialize caches... */
133 la t9, mips_cache_reset
137 /* ... and enable them */
138 li t0, CONFIG_SYS_MIPS_CACHE_MODE
142 /* Set up temporary stack */
143 li sp, CONFIG_SYS_INIT_SP_ADDR
151 * void relocate_code (addr_sp, gd, addr_moni)
153 * This "function" does not return, instead it continues in RAM
154 * after relocating the monitor code.
158 * a2 = destination address
163 move sp, a0 # set new stack pointer
166 move s0, a1 # save gd in s0
167 move s2, a2 # save destination address in s2
169 li t0, CONFIG_SYS_MONITOR_BASE
170 sub s1, s2, t0 # s1 <-- relocation offset
173 lw t2, -12(t3) # t2 <-- __image_copy_end
176 add gp, s1 # adjust gp
179 * t0 = source address
180 * t1 = target address
181 * t2 = source end address
190 /* If caches were enabled, we would have to flush them here. */
191 sub a1, t1, s2 # a1 <-- size
194 move a0, s2 # a0 <-- destination address
196 /* Jump to where we've relocated ourselves */
197 addi t0, s2, in_ram - _start
202 .word __rel_dyn_start
203 .word __image_copy_end
204 .word _GLOBAL_OFFSET_TABLE_
205 .word num_got_entries
209 * Now we want to update GOT.
211 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
212 * generated by GNU ld. Skip these reserved entries from relocation.
214 lw t3, -4(t0) # t3 <-- num_got_entries
215 lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
216 add t8, s1 # t8 now holds relocated _G_O_T_
217 addi t8, t8, 8 # skipping first two entries
229 /* Update dynamic relocations */
230 lw t1, -16(t0) # t1 <-- __rel_dyn_start
231 lw t2, -20(t0) # t2 <-- __rel_dyn_end
233 b 2f # skip first reserved entry
237 lw t8, -4(t1) # t8 <-- relocation info
240 bne t8, t3, 2f # skip non R_MIPS_REL32 entries
243 lw t3, -8(t1) # t3 <-- location to fix up in FLASH
245 lw t8, 0(t3) # t8 <-- original pointer
246 add t8, s1 # t8 <-- adjusted pointer
248 add t3, s1 # t3 <-- location to fix up in RAM
253 addi t1, 8 # each rel.dyn entry is 8 bytes
258 * GOT is now relocated. Thus __bss_start and __bss_end can be
259 * accessed directly via $gp.
261 la t1, __bss_start # t1 <-- __bss_start
262 la t2, __bss_end # t2 <-- __bss_end
269 move a0, s0 # a0 <-- gd