3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/mipsregs.h>
12 #include <asm/cacheops.h>
13 #include <asm/reboot.h>
15 #define cache_op(op, addr) \
16 __asm__ __volatile__( \
23 : "i" (op), "R" (*(unsigned char *)(addr)))
25 void __attribute__((weak)) _machine_restart(void)
27 fprintf(stderr, "*** reset failed ***\n");
33 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
40 void flush_cache(ulong start_addr, ulong size)
42 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
43 unsigned long addr = start_addr & ~(lsize - 1);
44 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
46 /* aend will be miscalculated when size is zero, so we return here */
51 cache_op(HIT_WRITEBACK_INV_D, addr);
52 cache_op(HIT_INVALIDATE_I, addr);
59 void flush_dcache_range(ulong start_addr, ulong stop)
61 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
62 unsigned long addr = start_addr & ~(lsize - 1);
63 unsigned long aend = (stop - 1) & ~(lsize - 1);
66 cache_op(HIT_WRITEBACK_INV_D, addr);
73 void invalidate_dcache_range(ulong start_addr, ulong stop)
75 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
76 unsigned long addr = start_addr & ~(lsize - 1);
77 unsigned long aend = (stop - 1) & ~(lsize - 1);
80 cache_op(HIT_INVALIDATE_D, addr);
87 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
89 write_c0_entrylo0(low0);
90 write_c0_pagemask(pagemask);
91 write_c0_entrylo1(low1);
93 write_c0_index(index);