2 * Startup Code for MIPS64 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
11 #include <asm/regdef.h>
12 #include <asm/mipsregs.h>
14 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
15 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
18 #ifdef CONFIG_SYS_LITTLE_ENDIAN
19 #define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
20 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
22 #define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
23 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
27 * For the moment disable interrupts, mark the kernel mode and
28 * set ST0_KX so that the CPU does not spit fire when using
31 .macro setup_c0_status set clr
34 or t0, ST0_CU0 | \set | 0x1f | \clr
47 /* U-boot entry point */
52 /* TLB refill, 32 bit task */
57 /* XTLB refill, 64 bit task */
62 /* Cache error exception */
67 /* General exception */
72 /* Catch interrupt exceptions */
77 /* EJTAG debug exception */
84 /* Clear watch registers */
85 dmtc0 zero, CP0_WATCHLO
86 dmtc0 zero, CP0_WATCHHI
88 /* WP(Watch Pending), SW0/1 should be cleared */
91 setup_c0_status ST0_KX 0
95 mtc0 zero, CP0_COMPARE
97 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
98 /* CONFIG0 register */
99 dli t0, CONF_CM_UNCACHED
104 * Initialize $gp, force 8 byte alignment of bal instruction to forbid
105 * the compiler to put nop's between bal and _gp. This is required to
106 * keep _gp and ra aligned to 8 byte.
115 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
116 /* Initialize any external memory */
117 dla t9, lowlevel_init
121 /* Initialize caches... */
122 dla t9, mips_cache_reset
126 /* ... and enable them */
127 dli t0, CONFIG_SYS_MIPS_CACHE_MODE
131 /* Set up temporary stack */
132 dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
140 * void relocate_code (addr_sp, gd, addr_moni)
142 * This "function" does not return, instead it continues in RAM
143 * after relocating the monitor code.
147 * a2 = destination address
152 move sp, a0 # set new stack pointer
155 move s0, a1 # save gd in s0
156 move s2, a2 # save destination address in s2
158 dli t0, CONFIG_SYS_MONITOR_BASE
159 dsub s1, s2, t0 # s1 <-- relocation offset
162 ld t2, -24(t3) # t2 <-- __image_copy_end
165 dadd gp, s1 # adjust gp
168 * t0 = source address
169 * t1 = target address
170 * t2 = source end address
179 /* If caches were enabled, we would have to flush them here. */
180 dsub a1, t1, s2 # a1 <-- size
183 move a0, s2 # a0 <-- destination address
185 /* Jump to where we've relocated ourselves */
186 daddi t0, s2, in_ram - _start
191 .dword __rel_dyn_start
192 .dword __image_copy_end
193 .dword _GLOBAL_OFFSET_TABLE_
194 .dword num_got_entries
198 * Now we want to update GOT.
200 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
201 * generated by GNU ld. Skip these reserved entries from relocation.
203 ld t3, -8(t0) # t3 <-- num_got_entries
204 ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
205 dadd t8, s1 # t8 now holds relocated _G_O_T_
206 daddi t8, t8, 16 # skipping first two entries
218 /* Update dynamic relocations */
219 ld t1, -32(t0) # t1 <-- __rel_dyn_start
220 ld t2, -40(t0) # t2 <-- __rel_dyn_end
222 b 2f # skip first reserved entry
226 lw t8, -4(t1) # t8 <-- relocation info
228 dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
229 bne t8, t3, 2f # skip non R_MIPS_REL32 entries
232 ld t3, -16(t1) # t3 <-- location to fix up in FLASH
234 ld t8, 0(t3) # t8 <-- original pointer
235 dadd t8, s1 # t8 <-- adjusted pointer
237 dadd t3, s1 # t3 <-- location to fix up in RAM
242 daddi t1, 16 # each rel.dyn entry is 16 bytes
247 * GOT is now relocated. Thus __bss_start and __bss_end can be
248 * accessed directly via $gp.
250 dla t1, __bss_start # t1 <-- __bss_start
251 dla t2, __bss_end # t2 <-- __bss_end
258 move a0, s0 # a0 <-- gd