2 * Startup Code for MIPS64 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
11 #include <asm/regdef.h>
12 #include <asm/mipsregs.h>
14 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
15 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
18 #ifndef CONFIG_SYS_INIT_SP_ADDR
19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
20 CONFIG_SYS_INIT_SP_OFFSET)
23 #ifdef CONFIG_SYS_LITTLE_ENDIAN
24 #define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
25 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
27 #define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32 * For the moment disable interrupts, mark the kernel mode and
33 * set ST0_KX so that the CPU does not spit fire when using
36 .macro setup_c0_status set clr
39 or t0, ST0_CU0 | \set | 0x1f | \clr
52 /* U-boot entry point */
57 /* TLB refill, 32 bit task */
62 /* XTLB refill, 64 bit task */
67 /* Cache error exception */
72 /* General exception */
77 /* Catch interrupt exceptions */
82 /* EJTAG debug exception */
89 /* Clear watch registers */
90 dmtc0 zero, CP0_WATCHLO
91 dmtc0 zero, CP0_WATCHHI
93 /* WP(Watch Pending), SW0/1 should be cleared */
96 setup_c0_status ST0_KX 0
100 mtc0 zero, CP0_COMPARE
102 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
103 /* CONFIG0 register */
104 dli t0, CONF_CM_UNCACHED
109 * Initialize $gp, force 8 byte alignment of bal instruction to forbid
110 * the compiler to put nop's between bal and _gp. This is required to
111 * keep _gp and ra aligned to 8 byte.
120 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
121 /* Initialize any external memory */
122 dla t9, lowlevel_init
126 /* Initialize caches... */
127 dla t9, mips_cache_reset
131 /* ... and enable them */
132 dli t0, CONFIG_SYS_MIPS_CACHE_MODE
136 /* Set up temporary stack */
137 dli sp, CONFIG_SYS_INIT_SP_ADDR
145 * void relocate_code (addr_sp, gd, addr_moni)
147 * This "function" does not return, instead it continues in RAM
148 * after relocating the monitor code.
152 * a2 = destination address
157 move sp, a0 # set new stack pointer
160 move s0, a1 # save gd in s0
161 move s2, a2 # save destination address in s2
163 dli t0, CONFIG_SYS_MONITOR_BASE
164 dsub s1, s2, t0 # s1 <-- relocation offset
167 ld t2, -24(t3) # t2 <-- __image_copy_end
170 dadd gp, s1 # adjust gp
173 * t0 = source address
174 * t1 = target address
175 * t2 = source end address
184 /* If caches were enabled, we would have to flush them here. */
185 dsub a1, t1, s2 # a1 <-- size
188 move a0, s2 # a0 <-- destination address
190 /* Jump to where we've relocated ourselves */
191 daddi t0, s2, in_ram - _start
196 .dword __rel_dyn_start
197 .dword __image_copy_end
198 .dword _GLOBAL_OFFSET_TABLE_
199 .dword num_got_entries
203 * Now we want to update GOT.
205 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
206 * generated by GNU ld. Skip these reserved entries from relocation.
208 ld t3, -8(t0) # t3 <-- num_got_entries
209 ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
210 dadd t8, s1 # t8 now holds relocated _G_O_T_
211 daddi t8, t8, 16 # skipping first two entries
223 /* Update dynamic relocations */
224 ld t1, -32(t0) # t1 <-- __rel_dyn_start
225 ld t2, -40(t0) # t2 <-- __rel_dyn_end
227 b 2f # skip first reserved entry
231 lw t8, -4(t1) # t8 <-- relocation info
233 dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
234 bne t8, t3, 2f # skip non R_MIPS_REL32 entries
237 ld t3, -16(t1) # t3 <-- location to fix up in FLASH
239 ld t8, 0(t3) # t8 <-- original pointer
240 dadd t8, s1 # t8 <-- adjusted pointer
242 dadd t3, s1 # t3 <-- location to fix up in RAM
247 daddi t1, 16 # each rel.dyn entry is 16 bytes
252 * GOT is now relocated. Thus __bss_start and __bss_end can be
253 * accessed directly via $gp.
255 dla t1, __bss_start # t1 <-- __bss_start
256 dla t2, __bss_end # t2 <-- __bss_end
263 move a0, s0 # a0 <-- gd