2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
15 #ifndef CONFIG_SYS_INIT_SP_ADDR
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
17 CONFIG_SYS_INIT_SP_OFFSET)
26 # ifdef CONFIG_SYS_LITTLE_ENDIAN
27 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
30 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
33 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34 # define STATUS_SET ST0_KX
40 MTC0 zero, CP0_WATCHLO,\sel
41 mtc0 t1, CP0_WATCHHI,\sel
42 mfc0 t0, CP0_WATCHHI,\sel
47 .macro uhi_mips_exception
48 move k0, t9 # preserve t9 in k0
49 move k1, a0 # preserve a0 in k1
50 li t9, 15 # UHI exception operation
51 li a0, 0 # Use hard register context
52 sdbbp 1 # Invoke UHI operation
57 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
58 and sp, t1, t0 # force 16 byte alignment
60 sp, sp, GD_SIZE # reserve space for gd
61 and sp, sp, t0 # force 16 byte alignment
62 move k0, sp # save gd pointer
63 #ifdef CONFIG_SYS_MALLOC_F_LEN
64 li t2, CONFIG_SYS_MALLOC_F_LEN
66 sp, sp, t2 # reserve space for early malloc
67 and sp, sp, t0 # force 16 byte alignment
78 #ifdef CONFIG_SYS_MALLOC_F_LEN
79 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
84 /* U-Boot entry point */
86 mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
88 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
90 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
91 * access external NOR flashes. If the board boots from NOR flash the
92 * internal BootROM does a blind read at address 0xB0000010 to read the
93 * initial configuration for that EBU in order to access the flash
94 * device with correct parameters. This config option is board-specific.
97 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
100 #if defined(CONFIG_MALTA)
102 * Linux expects the Board ID here.
105 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
109 #if defined(CONFIG_ROM_EXCEPTION_VECTORS)
111 * Exception vector entry points. When running from ROM, an exception
112 * cannot be handled. Halt execution and transfer control to debugger,
113 * if one is attached.
116 /* TLB refill, 32 bit task */
120 /* XTLB refill, 64 bit task */
124 /* Cache error exception */
128 /* General exception */
132 /* Catch interrupt exceptions */
136 /* EJTAG debug exception */
144 #if __mips_isa_rev >= 6
145 mfc0 t0, CP0_CONFIG, 5
146 and t0, t0, MIPS_CONF5_VP
151 mfc0 t0, CP0_GLOBALNUMBER
154 #ifdef CONFIG_ARCH_BMIPS
155 1: mfc0 t0, CP0_DIAGNOSTIC, 3
156 and t0, t0, (1 << 31)
158 1: mfc0 t0, CP0_EBASE
159 and t0, t0, EBASE_CPUNUM
162 /* Hang if this isn't the first CPU in the system */
169 /* Init CP0 Status */
170 4: mfc0 t0, CP0_STATUS
172 or t0, ST0_BEV | ST0_ERL | STATUS_SET
176 * Check whether CP0 Config1 is implemented. If not continue
177 * with legacy Watch register initialization.
184 * Check WR bit in CP0 Config1 to determine if Watch registers
187 mfc0 t0, CP0_CONFIG, 1
192 /* Clear Watch Status bits and disable watch exceptions */
193 li t1, 0x7 # Clear I, R and W conditions
206 MTC0 zero, CP0_WATCHLO
207 mtc0 zero, CP0_WATCHHI
210 /* Clear WP, IV and SW interrupts */
213 /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
214 mtc0 zero, CP0_COMPARE
216 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
218 and t0, t0, MIPS_CONF_IMPL
219 or t0, t0, CONF_CM_UNCACHED
225 * Initialize $gp, force pointer sized alignment of bal instruction to
226 * forbid the compiler to put nop's between bal and _gp. This is
227 * required to keep _gp and ra aligned to 8 byte.
236 #ifdef CONFIG_MIPS_CM
237 PTR_LA t9, mips_cm_map
242 #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
243 /* Set up initial stack and global data */
246 # ifdef CONFIG_DEBUG_UART
247 /* Earliest point to set up debug uart */
248 PTR_LA t9, debug_uart_init
254 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
255 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
256 /* Initialize any external memory */
257 PTR_LA t9, lowlevel_init
262 /* Initialize caches... */
263 PTR_LA t9, mips_cache_reset
267 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
268 /* Initialize any external memory */
269 PTR_LA t9, lowlevel_init
275 #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
276 /* Set up initial stack and global data */
279 # ifdef CONFIG_DEBUG_UART
280 /* Earliest point to set up debug uart */
281 PTR_LA t9, debug_uart_init
287 move a0, zero # a0 <-- boot_flags = 0
288 PTR_LA t9, board_init_f
296 * void relocate_code (addr_sp, gd, addr_moni)
298 * This "function" does not return, instead it continues in RAM
299 * after relocating the monitor code.
303 * a2 = destination address
306 move sp, a0 # set new stack pointer
309 move s0, a1 # save gd in s0
310 move s2, a2 # save destination address in s2
312 PTR_LI t0, CONFIG_SYS_MONITOR_BASE
313 PTR_SUB s1, s2, t0 # s1 <-- relocation offset
315 PTR_LA t2, __image_copy_end
319 * t0 = source address
320 * t1 = target address
321 * t2 = source end address
331 * Now we want to update GOT.
333 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
334 * generated by GNU ld. Skip these reserved entries from relocation.
336 PTR_LA t3, num_got_entries
337 PTR_LA t8, _GLOBAL_OFFSET_TABLE_
338 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
339 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
349 PTR_ADDIU t8, PTRSIZE
351 /* Update dynamic relocations */
352 PTR_LA t1, __rel_dyn_start
353 PTR_LA t2, __rel_dyn_end
355 b 2f # skip first reserved entry
356 PTR_ADDIU t1, 2 * PTRSIZE
359 lw t8, -4(t1) # t8 <-- relocation info
361 PTR_LI t3, MIPS_RELOC
362 bne t8, t3, 2f # skip non-MIPS_RELOC entries
365 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
367 PTR_L t8, 0(t3) # t8 <-- original pointer
368 PTR_ADD t8, s1 # t8 <-- adjusted pointer
370 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
375 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
378 * Flush caches to ensure our newly modified instructions are visible
379 * to the instruction cache. We're still running with the old GOT, so
380 * apply the reloc offset to the start address.
382 PTR_LA a0, __text_start
383 PTR_LA a1, __text_end
385 PTR_LA t9, flush_cache
389 PTR_ADD gp, s1 # adjust gp
394 * GOT is now relocated. Thus __bss_start and __bss_end can be
395 * accessed directly via $gp.
397 PTR_LA t1, __bss_start # t1 <-- __bss_start
398 PTR_LA t2, __bss_end # t2 <-- __bss_end
403 PTR_ADDIU t1, PTRSIZE
405 move a0, s0 # a0 <-- gd
407 PTR_LA t9, board_init_r