2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
15 #ifndef CONFIG_SYS_INIT_SP_ADDR
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
17 CONFIG_SYS_INIT_SP_OFFSET)
26 # ifdef CONFIG_SYS_LITTLE_ENDIAN
27 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
30 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
33 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34 # define STATUS_SET ST0_KX
38 * For the moment disable interrupts, mark the kernel mode and
39 * set ST0_KX so that the CPU does not spit fire when using
42 .macro setup_c0_status set clr
45 or t0, ST0_CU0 | \set | 0x1f | \clr
56 /* U-Boot entry point */
61 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
63 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
64 * access external NOR flashes. If the board boots from NOR flash the
65 * internal BootROM does a blind read at address 0xB0000010 to read the
66 * initial configuration for that EBU in order to access the flash
67 * device with correct parameters. This config option is board-specific.
69 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
71 #elif defined(CONFIG_MALTA)
73 * Linux expects the Board ID here.
75 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
80 /* TLB refill, 32 bit task */
85 /* XTLB refill, 64 bit task */
90 /* Cache error exception */
95 /* General exception */
100 /* Catch interrupt exceptions */
105 /* EJTAG debug exception */
112 /* Clear watch registers */
113 MTC0 zero, CP0_WATCHLO
114 mtc0 zero, CP0_WATCHHI
116 /* WP(Watch Pending), SW0/1 should be cleared */
119 setup_c0_status STATUS_SET 0
123 mtc0 zero, CP0_COMPARE
125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
127 and t0, t0, MIPS_CONF_IMPL
128 or t0, t0, CONF_CM_UNCACHED
133 * Initialize $gp, force pointer sized alignment of bal instruction to
134 * forbid the compiler to put nop's between bal and _gp. This is
135 * required to keep _gp and ra aligned to 8 byte.
144 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
145 /* Initialize any external memory */
146 PTR_LA t9, lowlevel_init
150 /* Initialize caches... */
151 PTR_LA t9, mips_cache_reset
156 /* Set up temporary stack */
158 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
159 and sp, t1, t0 # force 16 byte alignment
161 sp, sp, GD_SIZE # reserve space for gd
162 and sp, sp, t0 # force 16 byte alignment
163 move k0, sp # save gd pointer
164 #ifdef CONFIG_SYS_MALLOC_F_LEN
165 li t2, CONFIG_SYS_MALLOC_F_LEN
167 sp, sp, t2 # reserve space for early malloc
168 and sp, sp, t0 # force 16 byte alignment
177 PTR_ADDIU t0, PTRSIZE
179 #ifdef CONFIG_SYS_MALLOC_F_LEN
180 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
183 move a0, zero # a0 <-- boot_flags = 0
184 PTR_LA t9, board_init_f
191 * void relocate_code (addr_sp, gd, addr_moni)
193 * This "function" does not return, instead it continues in RAM
194 * after relocating the monitor code.
198 * a2 = destination address
201 move sp, a0 # set new stack pointer
204 move s0, a1 # save gd in s0
205 move s2, a2 # save destination address in s2
207 PTR_LI t0, CONFIG_SYS_MONITOR_BASE
208 PTR_SUB s1, s2, t0 # s1 <-- relocation offset
211 PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
214 PTR_ADD gp, s1 # adjust gp
217 * t0 = source address
218 * t1 = target address
219 * t2 = source end address
228 /* If caches were enabled, we would have to flush them here. */
229 PTR_SUB a1, t1, s2 # a1 <-- size
230 PTR_LA t9, flush_cache
232 move a0, s2 # a0 <-- destination address
234 /* Jump to where we've relocated ourselves */
235 PTR_ADDIU t0, s2, in_ram - _start
242 PTR _GLOBAL_OFFSET_TABLE_
247 * Now we want to update GOT.
249 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
250 * generated by GNU ld. Skip these reserved entries from relocation.
252 PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
253 PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
254 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
255 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
265 PTR_ADDIU t8, PTRSIZE
267 /* Update dynamic relocations */
268 PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
269 PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
271 b 2f # skip first reserved entry
272 PTR_ADDIU t1, 2 * PTRSIZE
275 lw t8, -4(t1) # t8 <-- relocation info
277 PTR_LI t3, MIPS_RELOC
278 bne t8, t3, 2f # skip non-MIPS_RELOC entries
281 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
283 PTR_L t8, 0(t3) # t8 <-- original pointer
284 PTR_ADD t8, s1 # t8 <-- adjusted pointer
286 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
291 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
296 * GOT is now relocated. Thus __bss_start and __bss_end can be
297 * accessed directly via $gp.
299 PTR_LA t1, __bss_start # t1 <-- __bss_start
300 PTR_LA t2, __bss_end # t2 <-- __bss_end
305 PTR_ADDIU t1, PTRSIZE
307 move a0, s0 # a0 <-- gd
309 PTR_LA t9, board_init_r