3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 * Xiangfu Liu <xiangfu@openmobilefree.net>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/mipsregs.h>
30 #include <asm/cacheops.h>
31 #include <asm/reboot.h>
33 #include <asm/jz4740.h>
35 #define cache_op(op, addr) \
36 __asm__ __volatile__( \
43 : "i" (op), "R" (*(unsigned char *)(addr)))
45 void __attribute__((weak)) _machine_restart(void)
47 struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
48 struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
51 /* wdt_select_extalclk() */
52 tmp = readw(&wdt->tcsr);
53 tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
54 tmp |= WDT_TCSR_EXT_EN;
55 writew(tmp, &wdt->tcsr);
57 /* wdt_select_clk_div64() */
58 tmp = readw(&wdt->tcsr);
59 tmp &= ~WDT_TCSR_PRESCALE_MASK;
60 tmp |= WDT_TCSR_PRESCALE64,
61 writew(tmp, &wdt->tcsr);
63 writew(100, &wdt->tdr); /* wdt_set_data(100) */
64 writew(0, &wdt->tcnt); /* wdt_set_count(0); */
65 writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
66 writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
72 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
76 fprintf(stderr, "*** reset failed ***\n");
80 void flush_cache(ulong start_addr, ulong size)
82 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
83 unsigned long addr = start_addr & ~(lsize - 1);
84 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
86 for (; addr <= aend; addr += lsize) {
87 cache_op(Hit_Writeback_Inv_D, addr);
88 cache_op(Hit_Invalidate_I, addr);
92 void flush_dcache_range(ulong start_addr, ulong stop)
94 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
95 unsigned long addr = start_addr & ~(lsize - 1);
96 unsigned long aend = (stop - 1) & ~(lsize - 1);
98 for (; addr <= aend; addr += lsize)
99 cache_op(Hit_Writeback_Inv_D, addr);
102 void invalidate_dcache_range(ulong start_addr, ulong stop)
104 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
105 unsigned long addr = start_addr & ~(lsize - 1);
106 unsigned long aend = (stop - 1) & ~(lsize - 1);
108 for (; addr <= aend; addr += lsize)
109 cache_op(Hit_Invalidate_D, addr);
112 void flush_icache_all(void)
116 __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
117 __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
119 for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
120 addr += CONFIG_SYS_CACHELINE_SIZE) {
121 cache_op(Index_Store_Tag_I, addr);
125 __asm__ __volatile__(
127 "mfc0 %0, $16, 7\n\t"
130 "mtc0 %0, $16, 7\n\t"
136 void flush_dcache_all(void)
140 for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
141 addr += CONFIG_SYS_CACHELINE_SIZE) {
142 cache_op(Index_Writeback_Inv_D, addr);
145 __asm__ __volatile__("sync");
148 void flush_cache_all(void)