git.sur5r.net Git - u-boot/blob - arch/mips/dts/brcm,bcm3380.dtsi

   1 /*
   2  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/bcm3380-clock.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/reset/bcm3380-reset.h>
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         compatible = "brcm,bcm3380";
  14
  15         cpus {
  16                 reg = <0x14e00000 0x4>;
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 u-boot,dm-pre-reloc;
  20
  21                 cpu@0 {
  22                         compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         u-boot,dm-pre-reloc;
  26                 };
  27
  28                 cpu@1 {
  29                         compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
  30                         device_type = "cpu";
  31                         reg = <1>;
  32                         u-boot,dm-pre-reloc;
  33                 };
  34         };
  35
  36         clocks {
  37                 compatible = "simple-bus";
  38                 #address-cells = <1>;
  39                 #size-cells = <1>;
  40                 u-boot,dm-pre-reloc;
  41
  42                 periph_osc: periph-osc {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <48000000>;
  46                         u-boot,dm-pre-reloc;
  47                 };
  48
  49                 periph_clk0: periph-clk@14e00004 {
  50                         compatible = "brcm,bcm6345-clk";
  51                         reg = <0x14e00004 0x4>;
  52                         #clock-cells = <1>;
  53                 };
  54
  55                 periph_clk1: periph-clk@14e00008 {
  56                         compatible = "brcm,bcm6345-clk";
  57                         reg = <0x14e00008 0x4>;
  58                         #clock-cells = <1>;
  59                 };
  60         };
  61
  62         ubus {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 u-boot,dm-pre-reloc;
  67
  68                 memory-controller@12000000 {
  69                         compatible = "brcm,bcm6328-mc";
  70                         reg = <0x12000000 0x1000>;
  71                         u-boot,dm-pre-reloc;
  72                 };
  73
  74                 periph_rst0: reset-controller@14e0008c {
  75                         compatible = "brcm,bcm6345-reset";
  76                         reg = <0x14e0008c 0x4>;
  77                         #reset-cells = <1>;
  78                 };
  79
  80                 periph_rst1: reset-controller@14e00090 {
  81                         compatible = "brcm,bcm6345-reset";
  82                         reg = <0x14e00090 0x4>;
  83                         #reset-cells = <1>;
  84                 };
  85
  86                 pll_cntl: syscon@14e00094 {
  87                         compatible = "syscon";
  88                         reg = <0x14e00094 0x4>;
  89                 };
  90
  91                 syscon-reboot {
  92                         compatible = "syscon-reboot";
  93                         regmap = <&pll_cntl>;
  94                         offset = <0x0>;
  95                         mask = <0x1>;
  96                 };
  97
  98                 wdt: watchdog@14e000dc {
  99                         compatible = "brcm,bcm6345-wdt";
 100                         reg = <0x14e000dc 0xc>;
 101
 102                         clocks = <&periph_osc>;
 103                 };
 104
 105                 wdt-reboot {
 106                         compatible = "wdt-reboot";
 107                         wdt = <&wdt>;
 108                 };
 109
 110                 gpio0: gpio-controller@14e00100 {
 111                         compatible = "brcm,bcm6345-gpio";
 112                         reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
 113                         gpio-controller;
 114                         #gpio-cells = <2>;
 115
 116                         status = "disabled";
 117                 };
 118
 119                 gpio1: gpio-controller@14e00104 {
 120                         compatible = "brcm,bcm6345-gpio";
 121                         reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
 122                         gpio-controller;
 123                         #gpio-cells = <2>;
 124                         ngpios = <3>;
 125
 126                         status = "disabled";
 127                 };
 128
 129                 uart0: serial@14e00200 {
 130                         compatible = "brcm,bcm6345-uart";
 131                         reg = <0x14e00200 0x18>;
 132                         clocks = <&periph_osc>;
 133
 134                         status = "disabled";
 135                 };
 136
 137                 uart1: serial@14e00220 {
 138                         compatible = "brcm,bcm6345-uart";
 139                         reg = <0x14e00220 0x18>;
 140                         clocks = <&periph_osc>;
 141
 142                         status = "disabled";
 143                 };
 144
 145                 leds: led-controller@14e00f00 {
 146                         compatible = "brcm,bcm6328-leds";
 147                         reg = <0x14e00f00 0x1c>;
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150
 151                         status = "disabled";
 152                 };
 153         };
 154 };