1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
6 #include <dt-bindings/clock/bcm6338-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/bcm6338-reset.h>
9 #include "skeleton.dtsi"
12 compatible = "brcm,bcm6338";
19 reg = <0xfffe0000 0x4>;
25 compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
33 compatible = "simple-bus";
38 periph_osc: periph-osc {
39 compatible = "fixed-clock";
41 clock-frequency = <50000000>;
45 periph_clk: periph-clk {
46 compatible = "brcm,bcm6345-clk";
47 reg = <0xfffe0004 0x4>;
52 pflash: nor@1fc00000 {
53 compatible = "cfi-flash";
54 reg = <0x1fc00000 0x400000>;
63 compatible = "simple-bus";
68 pll_cntl: syscon@fffe0008 {
69 compatible = "syscon";
70 reg = <0xfffe0008 0x4>;
74 compatible = "syscon-reboot";
80 periph_rst: reset-controller@fffe0028 {
81 compatible = "brcm,bcm6345-reset";
82 reg = <0xfffe0028 0x4>;
86 wdt: watchdog@fffe021c {
87 compatible = "brcm,bcm6345-wdt";
88 reg = <0xfffe021c 0xc>;
89 clocks = <&periph_osc>;
93 compatible = "wdt-reboot";
97 uart0: serial@fffe0300 {
98 compatible = "brcm,bcm6345-uart";
99 reg = <0xfffe0300 0x18>;
100 clocks = <&periph_osc>;
105 gpio: gpio-controller@fffe0404 {
106 compatible = "brcm,bcm6345-gpio";
107 reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
116 compatible = "brcm,bcm6348-spi";
117 reg = <0xfffe0c00 0xc0>;
118 #address-cells = <1>;
120 clocks = <&periph_clk BCM6338_CLK_SPI>;
121 resets = <&periph_rst BCM6338_RST_SPI>;
122 spi-max-frequency = <20000000>;
128 memory-controller@fffe3100 {
129 compatible = "brcm,bcm6338-mc";
130 reg = <0xfffe3100 0x38>;