git.sur5r.net Git - u-boot/blob - arch/mips/dts/brcm,bcm6338.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   4  */
   5
   6 #include <dt-bindings/clock/bcm6338-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/reset/bcm6338-reset.h>
   9 #include "skeleton.dtsi"
  10
  11 / {
  12         compatible = "brcm,bcm6338";
  13
  14         aliases {
  15                 spi0 = &spi;
  16         };
  17
  18         cpus {
  19                 reg = <0xfffe0000 0x4>;
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22                 u-boot,dm-pre-reloc;
  23
  24                 cpu@0 {
  25                         compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         u-boot,dm-pre-reloc;
  29                 };
  30         };
  31
  32         clocks {
  33                 compatible = "simple-bus";
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 u-boot,dm-pre-reloc;
  37
  38                 periph_osc: periph-osc {
  39                         compatible = "fixed-clock";
  40                         #clock-cells = <0>;
  41                         clock-frequency = <50000000>;
  42                         u-boot,dm-pre-reloc;
  43                 };
  44
  45                 periph_clk: periph-clk {
  46                         compatible = "brcm,bcm6345-clk";
  47                         reg = <0xfffe0004 0x4>;
  48                         #clock-cells = <1>;
  49                 };
  50         };
  51
  52         pflash: nor@1fc00000 {
  53                 compatible = "cfi-flash";
  54                 reg = <0x1fc00000 0x400000>;
  55                 bank-width = <2>;
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58
  59                 status = "disabled";
  60         };
  61
  62         ubus {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 u-boot,dm-pre-reloc;
  67
  68                 pll_cntl: syscon@fffe0008 {
  69                         compatible = "syscon";
  70                         reg = <0xfffe0008 0x4>;
  71                 };
  72
  73                 syscon-reboot {
  74                         compatible = "syscon-reboot";
  75                         regmap = <&pll_cntl>;
  76                         offset = <0x0>;
  77                         mask = <0x1>;
  78                 };
  79
  80                 periph_rst: reset-controller@fffe0028 {
  81                         compatible = "brcm,bcm6345-reset";
  82                         reg = <0xfffe0028 0x4>;
  83                         #reset-cells = <1>;
  84                 };
  85
  86                 wdt: watchdog@fffe021c {
  87                         compatible = "brcm,bcm6345-wdt";
  88                         reg = <0xfffe021c 0xc>;
  89                         clocks = <&periph_osc>;
  90                 };
  91
  92                 wdt-reboot {
  93                         compatible = "wdt-reboot";
  94                         wdt = <&wdt>;
  95                 };
  96
  97                 uart0: serial@fffe0300 {
  98                         compatible = "brcm,bcm6345-uart";
  99                         reg = <0xfffe0300 0x18>;
 100                         clocks = <&periph_osc>;
 101
 102                         status = "disabled";
 103                 };
 104
 105                 gpio: gpio-controller@fffe0404 {
 106                         compatible = "brcm,bcm6345-gpio";
 107                         reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
 108                         gpio-controller;
 109                         #gpio-cells = <2>;
 110                         ngpios = <8>;
 111
 112                         status = "disabled";
 113                 };
 114
 115                 spi: spi@fffe0c00 {
 116                         compatible = "brcm,bcm6348-spi";
 117                         reg = <0xfffe0c00 0xc0>;
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         clocks = <&periph_clk BCM6338_CLK_SPI>;
 121                         resets = <&periph_rst BCM6338_RST_SPI>;
 122                         spi-max-frequency = <20000000>;
 123                         num-cs = <4>;
 124
 125                         status = "disabled";
 126                 };
 127
 128                 memory-controller@fffe3100 {
 129                         compatible = "brcm,bcm6338-mc";
 130                         reg = <0xfffe3100 0x38>;
 131                         u-boot,dm-pre-reloc;
 132                 };
 133         };
 134 };