2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/bcm6338-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6338-reset.h>
10 #include "skeleton.dtsi"
13 compatible = "brcm,bcm6338";
16 reg = <0xfffe0000 0x4>;
22 compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
30 compatible = "simple-bus";
35 periph_osc: periph-osc {
36 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 periph_clk: periph-clk {
43 compatible = "brcm,bcm6345-clk";
44 reg = <0xfffe0004 0x4>;
49 pflash: nor@1fc00000 {
50 compatible = "cfi-flash";
51 reg = <0x1fc00000 0x400000>;
60 compatible = "simple-bus";
65 pll_cntl: syscon@fffe0008 {
66 compatible = "syscon";
67 reg = <0xfffe0008 0x4>;
71 compatible = "syscon-reboot";
77 periph_rst: reset-controller@fffe0028 {
78 compatible = "brcm,bcm6345-reset";
79 reg = <0xfffe0028 0x4>;
83 wdt: watchdog@fffe021c {
84 compatible = "brcm,bcm6345-wdt";
85 reg = <0xfffe021c 0xc>;
86 clocks = <&periph_osc>;
90 compatible = "wdt-reboot";
94 uart0: serial@fffe0300 {
95 compatible = "brcm,bcm6345-uart";
96 reg = <0xfffe0300 0x18>;
97 clocks = <&periph_osc>;
102 gpio: gpio-controller@fffe0404 {
103 compatible = "brcm,bcm6345-gpio";
104 reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
112 memory-controller@fffe3100 {
113 compatible = "brcm,bcm6338-mc";
114 reg = <0xfffe3100 0x38>;