2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/bcm6338-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6338-reset.h>
10 #include "skeleton.dtsi"
13 compatible = "brcm,bcm6338";
20 reg = <0xfffe0000 0x4>;
26 compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
34 compatible = "simple-bus";
39 periph_osc: periph-osc {
40 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
46 periph_clk: periph-clk {
47 compatible = "brcm,bcm6345-clk";
48 reg = <0xfffe0004 0x4>;
53 pflash: nor@1fc00000 {
54 compatible = "cfi-flash";
55 reg = <0x1fc00000 0x400000>;
64 compatible = "simple-bus";
69 pll_cntl: syscon@fffe0008 {
70 compatible = "syscon";
71 reg = <0xfffe0008 0x4>;
75 compatible = "syscon-reboot";
81 periph_rst: reset-controller@fffe0028 {
82 compatible = "brcm,bcm6345-reset";
83 reg = <0xfffe0028 0x4>;
87 wdt: watchdog@fffe021c {
88 compatible = "brcm,bcm6345-wdt";
89 reg = <0xfffe021c 0xc>;
90 clocks = <&periph_osc>;
94 compatible = "wdt-reboot";
98 uart0: serial@fffe0300 {
99 compatible = "brcm,bcm6345-uart";
100 reg = <0xfffe0300 0x18>;
101 clocks = <&periph_osc>;
106 gpio: gpio-controller@fffe0404 {
107 compatible = "brcm,bcm6345-gpio";
108 reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
117 compatible = "brcm,bcm6348-spi";
118 reg = <0xfffe0c00 0xc0>;
119 #address-cells = <1>;
121 clocks = <&periph_clk BCM6338_CLK_SPI>;
122 resets = <&periph_rst BCM6338_RST_SPI>;
123 spi-max-frequency = <20000000>;
129 memory-controller@fffe3100 {
130 compatible = "brcm,bcm6338-mc";
131 reg = <0xfffe3100 0x38>;