git.sur5r.net Git - u-boot/blob - arch/mips/dts/brcm,bcm6358.dtsi

   1 /*
   2  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/bcm6358-clock.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/reset/bcm6358-reset.h>
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         compatible = "brcm,bcm6358";
  14
  15         cpus {
  16                 reg = <0xfffe0000 0x4>;
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 u-boot,dm-pre-reloc;
  20
  21                 cpu@0 {
  22                         compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         u-boot,dm-pre-reloc;
  26                 };
  27
  28                 cpu@1 {
  29                         compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
  30                         device_type = "cpu";
  31                         reg = <1>;
  32                         u-boot,dm-pre-reloc;
  33                 };
  34         };
  35
  36         clocks {
  37                 compatible = "simple-bus";
  38                 #address-cells = <1>;
  39                 #size-cells = <1>;
  40                 u-boot,dm-pre-reloc;
  41
  42                 periph_osc: periph-osc {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <50000000>;
  46                         u-boot,dm-pre-reloc;
  47                 };
  48
  49                 periph_clk: periph-clk {
  50                         compatible = "brcm,bcm6345-clk";
  51                         reg = <0xfffe0004 0x4>;
  52                         #clock-cells = <1>;
  53                 };
  54         };
  55
  56         pflash: nor@1e000000 {
  57                 compatible = "cfi-flash";
  58                 reg = <0x1e000000 0x2000000>;
  59                 bank-width = <2>;
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62
  63                 status = "disabled";
  64         };
  65
  66         ubus {
  67                 compatible = "simple-bus";
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 u-boot,dm-pre-reloc;
  71
  72                 pll_cntl: syscon@fffe0008 {
  73                         compatible = "syscon";
  74                         reg = <0xfffe0008 0x4>;
  75                 };
  76
  77                 syscon-reboot {
  78                         compatible = "syscon-reboot";
  79                         regmap = <&pll_cntl>;
  80                         offset = <0x0>;
  81                         mask = <0x1>;
  82                 };
  83
  84                 periph_rst: reset-controller@fffe0034 {
  85                         compatible = "brcm,bcm6345-reset";
  86                         reg = <0xfffe0034 0x4>;
  87                         #reset-cells = <1>;
  88                 };
  89
  90                 gpio1: gpio-controller@fffe0080 {
  91                         compatible = "brcm,bcm6345-gpio";
  92                         reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
  93                         gpio-controller;
  94                         #gpio-cells = <2>;
  95                         ngpios = <8>;
  96
  97                         status = "disabled";
  98                 };
  99
 100                 gpio0: gpio-controller@fffe0084 {
 101                         compatible = "brcm,bcm6345-gpio";
 102                         reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>;
 103                         gpio-controller;
 104                         #gpio-cells = <2>;
 105
 106                         status = "disabled";
 107                 };
 108
 109                 leds: led-controller@fffe00d0 {
 110                         compatible = "brcm,bcm6358-leds";
 111                         reg = <0xfffe00d0 0x8>;
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114
 115                         status = "disabled";
 116                 };
 117
 118                 uart0: serial@fffe0100 {
 119                         compatible = "brcm,bcm6345-uart";
 120                         reg = <0xfffe0100 0x18>;
 121                         clocks = <&periph_osc>;
 122
 123                         status = "disabled";
 124                 };
 125
 126                 uart1: serial@fffe0120 {
 127                         compatible = "brcm,bcm6345-uart";
 128                         reg = <0xfffe0120 0x18>;
 129                         clocks = <&periph_osc>;
 130
 131                         status = "disabled";
 132                 };
 133
 134                 memory-controller@fffe1200 {
 135                         compatible = "brcm,bcm6358-mc";
 136                         reg = <0xfffe1200 0x1000>;
 137                         u-boot,dm-pre-reloc;
 138                 };
 139         };
 140 };