2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __MIPS_CACHE_H__
8 #define __MIPS_CACHE_H__
11 * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use
12 * that as a default for aligning DMA buffers unless the board config has
13 * specified another cache line size.
15 #ifdef CONFIG_SYS_CACHELINE_SIZE
16 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
18 #define ARCH_DMA_MINALIGN 128
21 #endif /* __MIPS_CACHE_H__ */