1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * Based on Atheros LSDK/QSDK and u-boot_mod project
9 #include <asm/regdef.h>
10 #include <asm/mipsregs.h>
11 #include <asm/addrspace.h>
12 #include <mach/ar71xx_regs.h>
14 #define SET_BIT(val, bit) ((val) | (1 << (bit)))
15 #define SET_PLL_PD(val) SET_BIT(val, 30)
16 #define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
17 #define PLL_BYPASS(val) SET_BIT(val, 2)
19 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \
20 (((0x3F & divint) << 10) | \
21 ((0x1F & refdiv) << 16) | \
22 ((0x1 & range) << 21) | \
23 ((0x7 & outdiv) << 23) )
25 #define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
26 (((0x3 & (cpudiv - 1)) << 5) | \
27 ((0x3 & (ddrdiv - 1)) << 10) | \
28 ((0x3 & (ahbdiv - 1)) << 15) )
33 * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
34 * After PLL configuration we need to clear this bit
36 * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
38 * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL)
39 * => 32 (0x20) VCOOUT = XTAL * DIV_INT
40 * bits 16..20 (5bit) REFDIV (Reference clock divider)
41 * => 1 (0x1) [Must start at values 1]
42 * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL)
43 * => 0 (0x0) [Doesn't impact clock values]
44 * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output)
45 * => 1 (0x1) [0 is illegal!]
46 * PLLOUT = VCOOUT * (1/2^OUTDIV)
48 /* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
49 #define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1)
50 /* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
51 #define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1)
56 * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
57 * After PLL configuration we need to clear this bit
59 * Values written into CPU Clock Control Register CLOCK_CONTROL
61 * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.
62 * Software must enable the CPU PLL for normal and
63 * then set this bit to 0)
64 * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
65 * CPU_CLK = PLLOUT / CPU_POST_DIV
66 * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
67 * DDR_CLK = PLLOUT / DDR_POST_DIV
68 * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
69 * AHB_CLK = PLLOUT / AHB_POST_DIV
72 #define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
78 /* These three WLAN_RESET will avoid original issue */
81 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
82 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
84 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
86 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
89 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
100 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
106 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
110 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
112 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
118 sw t1, AR933X_RTC_REG_RESET(t0)
123 sw t1, AR933X_RTC_REG_RESET(t0)
127 /* Wait for RTC in on state */
129 lw t1, AR933X_RTC_REG_STATUS(t0)
135 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
136 andi t1, t5, 0x01 # t5 BOOT_STRAP
145 sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
147 /* Program phase shift */
148 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
153 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
156 /* in some cases, the SoC doesn't start with higher clock on AHB */
157 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
158 li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
159 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
162 /* Set SETTLE_TIME in CPU PLL */
163 andi t1, t5, 0x01 # t5 BOOT_STRAP
172 sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
175 /* Set nint, frac, refdiv, outdiv, range according to xtal */
177 andi t1, t5, 0x01 # t5 BOOT_STRAP
180 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
184 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
186 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
189 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
195 /* Put frac bit19:10 configuration */
197 sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
200 /* Clear PLL power down bit in CPU PLL configuration */
201 andi t1, t5, 0x01 # t5 BOOT_STRAP
204 li t1, PLL_CPU_CONFIG_VAL_25M
208 li t1, PLL_CPU_CONFIG_VAL_40M
210 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
213 /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
215 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
221 /* Confirm DDR PLL lock */
233 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
234 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
237 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
249 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
252 /* Check meas_done */
254 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
259 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
270 /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
271 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
272 li t1, PLL_CLK_CONTROL_VAL
273 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)