git.sur5r.net Git - u-boot/blob - arch/mips/mach-ath79/qca953x/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
   4  * Based on Atheros LSDK/QSDK
   5  */
   6
   7 #include <config.h>
   8 #include <asm/asm.h>
   9 #include <asm/regdef.h>
  10 #include <asm/mipsregs.h>
  11 #include <asm/addrspace.h>
  12 #include <mach/ar71xx_regs.h>
  13
  14 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \
  15      (((0x3F & divint) << 10) | \
  16      ((0x1F & refdiv) << 16) | \
  17      ((0x1 & range)   << 21) | \
  18      ((0x7 & outdiv)  << 23) )
  19
  20 #define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
  21     (((0x3 & (cpudiv - 1)) << 5)  | \
  22     ((0x3 & (ddrdiv - 1)) << 10) | \
  23     ((0x3 & (ahbdiv - 1)) << 15) )
  24
  25 #define SET_FIELD(name, v)      (((v) & QCA953X_##name##_MASK) << \
  26                                  QCA953X_##name##_SHIFT)
  27
  28 #define DPLL2_KI(v)             SET_FIELD(SRIF_DPLL2_KI, v)
  29 #define DPLL2_KD(v)             SET_FIELD(SRIF_DPLL2_KD, v)
  30 #define DPLL2_PWD               QCA953X_SRIF_DPLL2_PWD
  31 #define MK_DPLL2(ki, kd)        (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD)
  32
  33 #define PLL_CPU_NFRAC(v)        SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)
  34 #define PLL_CPU_NINT(v)         SET_FIELD(PLL_CPU_CONFIG_NINT, v)
  35 #define PLL_CPU_REFDIV(v)       SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)
  36 #define PLL_CPU_OUTDIV(v)       SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)
  37 #define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
  38                                 (PLL_CPU_NFRAC(frac) | \
  39                                  PLL_CPU_NINT(nint) | \
  40                                  PLL_CPU_REFDIV(ref) | \
  41                                  PLL_CPU_OUTDIV(outdiv))
  42
  43 #define PLL_DDR_NFRAC(v)        SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)
  44 #define PLL_DDR_NINT(v)         SET_FIELD(PLL_DDR_CONFIG_NINT, v)
  45 #define PLL_DDR_REFDIV(v)       SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)
  46 #define PLL_DDR_OUTDIV(v)       SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)
  47 #define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
  48                                 (PLL_DDR_NFRAC(frac) | \
  49                                  PLL_DDR_REFDIV(ref) | \
  50                                  PLL_DDR_NINT(nint) | \
  51                                  PLL_DDR_OUTDIV(outdiv) | \
  52                                  QCA953X_PLL_CONFIG_PWD)
  53
  54 #define PLL_CPU_CONF_VAL        MK_PLL_CPU_CONF(0, 26, 1, 0)
  55 #define PLL_DDR_CONF_VAL        MK_PLL_DDR_CONF(0, 15, 1, 0)
  56
  57 #define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \
  58                                  QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \
  59                                  QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  60
  61 #define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)
  62 #define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)
  63 #define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)
  64 #define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \
  65                                 (PLL_CLK_CTRL_CPU_DIV(cpu) | \
  66                                  PLL_CLK_CTRL_DDR_DIV(ddr) | \
  67                                  PLL_CLK_CTRL_AHB_DIV(ahb))
  68 #define PLL_CLK_CTRL_VAL    (MK_PLL_CLK_CTRL(0, 0, 2) | \
  69                              PLL_CLK_CTRL_PLL_BYPASS | \
  70                              QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \
  71                              QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
  72
  73 #define PLL_DDR_DIT_FRAC_MAX(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)
  74 #define PLL_DDR_DIT_FRAC_MIN(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)
  75 #define PLL_DDR_DIT_FRAC_STEP(v)    SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)
  76 #define PLL_DDR_DIT_UPD_CNT(v)      SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)
  77 #define PLL_CPU_DIT_FRAC_MAX(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)
  78 #define PLL_CPU_DIT_FRAC_MIN(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)
  79 #define PLL_CPU_DIT_FRAC_STEP(v)    SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)
  80 #define PLL_CPU_DIT_UPD_CNT(v)      SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)
  81 #define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \
  82                                 (QCA953X_PLL_DIT_FRAC_EN | \
  83                                  PLL_DDR_DIT_FRAC_MAX(max) | \
  84                                  PLL_DDR_DIT_FRAC_MIN(min) | \
  85                                  PLL_DDR_DIT_FRAC_STEP(step) | \
  86                                  PLL_DDR_DIT_UPD_CNT(cnt))
  87 #define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \
  88                                 (QCA953X_PLL_DIT_FRAC_EN | \
  89                                  PLL_CPU_DIT_FRAC_MAX(max) | \
  90                                  PLL_CPU_DIT_FRAC_MIN(min) | \
  91                                  PLL_CPU_DIT_FRAC_STEP(step) | \
  92                                  PLL_CPU_DIT_UPD_CNT(cnt))
  93 #define PLL_CPU_DIT_FRAC_VAL    MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
  94 #define PLL_DDR_DIT_FRAC_VAL    MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)
  95
  96     .text
  97     .set noreorder
  98
  99 LEAF(lowlevel_init)
 100         /* RTC Reset */
 101         li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
 102         lw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
 103         li      t2, 0x08000000
 104         or      t1, t1, t2
 105         sw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
 106         nop
 107         lw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
 108         li      t2, 0xf7ffffff
 109         and     t1, t1, t2
 110         sw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
 111         nop
 112
 113         /* RTC Force Wake */
 114         li      t0, CKSEG1ADDR(QCA953X_RTC_BASE)
 115         li      t1, 0x01
 116         sw      t1, QCA953X_RTC_REG_SYNC_RESET(t0)
 117         nop
 118         nop
 119
 120         /* Wait for RTC in on state */
 121 1:
 122         lw      t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
 123         andi    t1, t1, 0x02
 124         beqz    t1, 1b
 125         nop
 126
 127         li      t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
 128         li      t1, MK_DPLL2(2, 16)
 129         sw      t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
 130         sw      t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
 131         sw      t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
 132         sw      t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
 133
 134         li      t0, CKSEG1ADDR(AR71XX_PLL_BASE)
 135         lw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
 136         ori     t1, PLL_CLK_CTRL_PLL_BYPASS
 137         sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
 138         nop
 139
 140         li      t1, PLL_CPU_CONF_VAL
 141         sw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
 142         nop
 143
 144         li      t1, PLL_DDR_CONF_VAL
 145         sw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
 146         nop
 147
 148         li      t1, PLL_CLK_CTRL_VAL
 149         sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
 150         nop
 151
 152         lw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
 153         li      t2, ~QCA953X_PLL_CONFIG_PWD
 154         and     t1, t1, t2
 155         sw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
 156         nop
 157
 158         lw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
 159         li      t2, ~QCA953X_PLL_CONFIG_PWD
 160         and     t1, t1, t2
 161         sw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
 162         nop
 163
 164         lw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
 165         li      t2, ~PLL_CLK_CTRL_PLL_BYPASS
 166         and     t1, t1, t2
 167         sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
 168         nop
 169
 170         li      t1, PLL_DDR_DIT_FRAC_VAL
 171         sw      t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
 172         nop
 173
 174         li      t1, PLL_CPU_DIT_FRAC_VAL
 175         sw      t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
 176         nop
 177
 178         li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
 179         lui     t1, 0x03fc
 180         sw      t1, 0xb4(t0)
 181
 182         nop
 183         jr ra
 184          nop
 185     END(lowlevel_init)