2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/addrspace.h>
11 #include <asm/types.h>
12 #include <mach/ath79.h>
13 #include <mach/ar71xx_regs.h>
15 void _machine_restart(void)
20 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
23 reg = AR71XX_RESET_REG_RESET_MODULE;
24 else if (soc_is_ar724x())
25 reg = AR724X_RESET_REG_RESET_MODULE;
26 else if (soc_is_ar913x())
27 reg = AR913X_RESET_REG_RESET_MODULE;
28 else if (soc_is_ar933x())
29 reg = AR933X_RESET_REG_RESET_MODULE;
30 else if (soc_is_ar934x())
31 reg = AR934X_RESET_REG_RESET_MODULE;
32 else if (soc_is_qca953x())
33 reg = QCA953X_RESET_REG_RESET_MODULE;
34 else if (soc_is_qca955x())
35 reg = QCA955X_RESET_REG_RESET_MODULE;
36 else if (soc_is_qca956x())
37 reg = QCA956X_RESET_REG_RESET_MODULE;
39 puts("Reset register not defined for this SOC\n");
42 setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
48 u32 get_bootstrap(void)
53 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
56 reg = AR933X_RESET_REG_BOOTSTRAP;
57 else if (soc_is_ar934x())
58 reg = AR934X_RESET_REG_BOOTSTRAP;
59 else if (soc_is_qca953x())
60 reg = QCA953X_RESET_REG_BOOTSTRAP;
61 else if (soc_is_qca955x())
62 reg = QCA955X_RESET_REG_BOOTSTRAP;
63 else if (soc_is_qca956x())
64 reg = QCA956X_RESET_REG_BOOTSTRAP;
66 puts("Bootstrap register not defined for this SOC\n");
69 return readl(base + reg);
74 static int usb_reset_ar933x(void __iomem *reset_regs)
76 /* Ungate the USB block */
77 setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
78 AR933X_RESET_USBSUS_OVERRIDE);
80 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
81 AR933X_RESET_USB_HOST);
83 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
84 AR933X_RESET_USB_PHY);
90 static int usb_reset_ar934x(void __iomem *reset_regs)
92 /* Ungate the USB block */
93 setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
94 AR934X_RESET_USBSUS_OVERRIDE);
96 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
97 AR934X_RESET_USB_PHY);
99 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
100 AR934X_RESET_USB_PHY_ANALOG);
102 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
103 AR934X_RESET_USB_HOST);
109 int ath79_usb_reset(void)
111 void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
112 AR71XX_USB_CTRL_SIZE,
114 void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
118 * Turn on the Buff and Desc swap bits.
119 * NOTE: This write into an undocumented register in mandatory to
120 * get the USB controller operational in BigEndian mode.
122 writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
125 return usb_reset_ar933x(reset_regs);
127 return usb_reset_ar934x(reset_regs);