1 // SPDX-License-Identifier: GPL-2.0+
5 * Hardcoded to UART 0 for now
6 * Speed and options also hardcoded to 115200 8N1
8 * Copyright (c) 2003 Thomas.Lange@corelatus.se
13 #include <mach/au1x00.h>
15 #include <linux/compiler.h>
17 /******************************************************************************
19 * serial_init - initialize a channel
21 * This routine initializes the number of data bits, parity
22 * and set the selected baud rate. Interrupts are disabled.
23 * Set the modem control signals if the option is selected.
28 static int au1x00_serial_init(void)
30 volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
31 volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
33 /* Enable clocks first */
34 *uart_enable = UART_EN_CE;
36 /* Then release reset */
37 /* Must release reset before setting other regs */
38 *uart_enable = UART_EN_CE|UART_EN_E;
40 /* Activate fifos, reset tx and rx */
41 /* Set tx trigger level to 12 */
42 *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
43 UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
51 static void au1x00_serial_setbrg(void)
53 volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
54 volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
55 volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
59 /* sd is system clock divisor */
60 /* see section 10.4.5 in au1550 datasheet */
61 sd = (*sys_powerctrl & 0x03) + 2;
63 /* calulate 2x baudrate and round */
64 divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
67 divisorx2 = divisorx2 + 1;
69 *uart_clk = divisorx2 / 2;
71 /* Set parity, stop bits and word length to 8N1 */
72 *uart_lcr = UART_LCR_WLEN8;
75 static void au1x00_serial_putc(const char c)
77 volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
78 volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
81 au1x00_serial_putc('\r');
83 /* Wait for fifo to shift out some bytes */
84 while((*uart_lsr&UART_LSR_THRE)==0);
89 static int au1x00_serial_getc(void)
91 volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
94 while (!serial_tstc());
100 static int au1x00_serial_tstc(void)
102 volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
104 if(*uart_lsr&UART_LSR_DR){
111 static struct serial_device au1x00_serial_drv = {
112 .name = "au1x00_serial",
113 .start = au1x00_serial_init,
115 .setbrg = au1x00_serial_setbrg,
116 .putc = au1x00_serial_putc,
117 .puts = default_serial_puts,
118 .getc = au1x00_serial_getc,
119 .tstc = au1x00_serial_tstc,
122 void au1x00_serial_initialize(void)
124 serial_register(&au1x00_serial_drv);
127 __weak struct serial_device *default_serial_console(void)
129 return &au1x00_serial_drv;