3 * Purna Chandra Mandal <purna.mandal@microchip.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <mach/pic32.h>
13 #include <dt-bindings/clock/microchip,clock.h>
22 #define CLK_MHZ(x) ((x) / 1000000)
24 DECLARE_GLOBAL_DATA_PTR;
26 static ulong clk_get_cpu_rate(void)
31 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
33 panic("uclass-clk: device not found\n");
37 return clk_get_rate(dev);
40 /* initialize prefetch module related to cpu_clk */
41 static void prefetch_init(void)
43 struct pic32_reg_atomic *regs;
44 const void __iomem *base;
48 /* cpu frequency in MHZ */
49 rate = clk_get_cpu_rate() / 1000000;
51 /* get flash ECC type */
52 base = pic32_get_syscfg_base();
53 v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
71 regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
72 writel(nr_waits, ®s->raw);
74 /* Enable prefetch for all */
75 writel(0x30, ®s->set);
79 /* arch specific CPU init after DM */
80 int arch_cpu_init_dm(void)
87 /* Un-gate DDR2 modules (gated by default) */
88 static void ddr2_pmd_ungate(void)
92 regs = pic32_get_syscfg_base();
93 writel(0, regs + PMD7);
96 /* initialize the DDR2 Controller and DDR2 PHY */
97 phys_size_t initdram(int board_type)
102 return ddr2_calculate_size();
105 int misc_init_r(void)
111 #ifdef CONFIG_DISPLAY_BOARDINFO
112 const char *get_core_name(void)
117 proc_id = read_c0_prid();
129 #ifdef CONFIG_CMD_CLK
130 int soc_clk_dump(void)
135 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
137 printf("clk-uclass not found\n");
141 printf("PLL Speed: %lu MHz\n",
142 CLK_MHZ(clk_get_periph_rate(dev, PLLCLK)));
143 printf("CPU Speed: %lu MHz\n", CLK_MHZ(clk_get_rate(dev)));
144 printf("MPLL Speed: %lu MHz\n",
145 CLK_MHZ(clk_get_periph_rate(dev, MPLL)));
147 for (i = PB1CLK; i <= PB7CLK; i++)
148 printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
149 CLK_MHZ(clk_get_periph_rate(dev, i)));
151 for (i = REF1CLK; i <= REF5CLK; i++)
152 printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
153 CLK_MHZ(clk_get_periph_rate(dev, i)));