3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
9 * Copyright (C) 2011 Andes Technology Corporation
10 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
11 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 /* CPU specific code */
36 #include <asm/cache.h>
38 #include <faraday/ftwdt010_wdt.h>
41 * cleanup_before_linux() is called just before we call linux
42 * it prepares the processor for linux
44 * we disable interrupt and caches.
46 int cleanup_before_linux(void)
51 /* turn off I/D-cache */
63 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
68 * reset to the base addr of andesboot.
69 * currently no ROM loader at addr 0.
70 * do not use reset_cpu(0);
72 #ifdef CONFIG_FTWDT010_WATCHDOG
74 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
75 * automatic hardware reset when booting Linux.
76 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
81 #endif /* CONFIG_FTWDT010_WATCHDOG */
86 static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
89 return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
90 >> ICM_CFG_OFF_ISZ) - 1);
92 return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
93 >> DCM_CFG_OFF_DSZ) - 1);
96 void dcache_flush_range(unsigned long start, unsigned long end)
98 unsigned long line_size;
100 line_size = CACHE_LINE_SIZE(DCACHE);
102 while (end > start) {
103 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
104 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
109 void icache_inval_range(unsigned long start, unsigned long end)
111 unsigned long line_size;
113 line_size = CACHE_LINE_SIZE(ICACHE);
114 while (end > start) {
115 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
120 void flush_cache(unsigned long addr, unsigned long size)
122 dcache_flush_range(addr, addr + size);
123 icache_inval_range(addr, addr + size);
126 void icache_enable(void)
128 __asm__ __volatile__ (
130 "ori $p0, $p0, 0x01\n\t"
136 void icache_disable(void)
138 __asm__ __volatile__ (
141 "and $p0, $p0, $p1\n\t"
147 int icache_status(void)
151 __asm__ __volatile__ (
153 "andi %0, $p0, 0x01\n\t"
162 void dcache_enable(void)
164 __asm__ __volatile__ (
166 "ori $p0, $p0, 0x02\n\t"
172 void dcache_disable(void)
174 __asm__ __volatile__ (
177 "and $p0, $p0, $p1\n\t"
183 int dcache_status(void)
187 __asm__ __volatile__ (
189 "andi %0, $p0, 0x02\n\t"