2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/macro.h>
15 #include <generated/asm-offsets.h>
18 * parameters for the SDRAM controller
20 #define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
21 #define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
22 #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
23 #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
24 #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
25 #define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
27 #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
28 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
29 #define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
30 #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
32 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
33 #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
36 * parameters for the static memory controller
38 #define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
39 #define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
41 #define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
42 #define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
45 * parameters for the ahbc controller
47 #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
48 #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
50 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
53 * parameters for the pmu controoler
55 #define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
58 * numeric 7 segment display
61 write32 CONFIG_DEBUG_LED, \num
65 * Waiting for SDRAM to set up
68 li $r0, CONFIG_FTSDMC021_BASE
70 lwi $r1, [$r0+FTSDMC021_CR2]
74 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
85 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
98 * There are 2 bank connected to FTSMC020 on AG101
99 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
100 * we need to set onboard SDRAM before remap and relocation.
103 write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052
104 write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151
107 * config AHB Controller
110 write32 AHBC_BSR6_A, AHBC_BSR6_D
113 * config PMU controller
115 /* ftpmu010_dlldis_disable, must do it in lowleve_init */
117 setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
120 * config SDRAM controller
123 write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
125 write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
127 write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
130 write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
134 write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
138 write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
147 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
154 #endif /* __NDS32_N1213_43U1H__ */
160 write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
161 write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001140
163 /* clear empty BSR registers */
165 li $r4, CONFIG_FTSDMC021_BASE
167 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
168 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
170 #ifdef CONFIG_MEM_REMAP
172 * Copy ROM code to SDRAM base for memory remap layout.
173 * This is not the real relocation, the real relocation is the function
174 * relocate_code() is start.S which supports the systems is memory
178 * Doing memory remap is essential for preparing some non-OS or RTOS
181 * This is also a must on ADP-AG101 board.
182 * The reason is because the ROM/FLASH circuit on PCB board.
183 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
184 * ROM/FLASH is used to boot.
186 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
187 * and the FLASH is connected to BANK1.
188 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
189 * and the FLASH is connected to BANK0.
190 * It will occur problem when doing flash probing if the flash is at
191 * BANK0 (0x00000000) while memory remapping was skipped.
193 * Other board like ADP-AG101P may not enable this since there is only
194 * a FLASH connected to bank0.
197 li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
199 la $r1, relo_base /* get $pc or $lp */
201 sethi $r6, hi20(_end)
202 ori $r6, $r6, lo12(_end)
211 * MEM remap bit is operational
212 * - use it to map writeable memory at 0x00000000, in place of flash
213 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
214 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
217 write32 SDMC_B0_BSR_A, 0x00001000
218 write32 SDMC_B1_BSR_A, 0x00001040
219 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
221 #endif /* #ifdef CONFIG_MEM_REMAP */
228 * Some of Andes CPU version support FPU coprocessor, if so,
229 * and toolchain support FPU instruction set, we should enable it.
231 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
233 mfsr $r0, $CPU_VER /* enable FPU if it exists */
236 beqz $r0, 1f /* skip if no COP */
237 mfsr $r0, $FUCOP_EXIST
239 beqz $r0, 1f /* skip if no FPU */
249 li $r8, (CONFIG_DEBUG_LED)
252 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */