2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/macro.h>
15 #include <generated/asm-offsets.h>
18 * parameters for the SDRAM controller
20 #define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
21 #define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
22 #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
23 #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
24 #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
26 #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
27 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
28 #define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
29 #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
31 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
34 * parameters for the static memory controller
36 #define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
37 #define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
39 #define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
40 #define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
43 * parameters for the ahbc controller
45 #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
46 #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
48 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
51 * parameters for the pmu controoler
53 #define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
56 * numeric 7 segment display
59 write32 CONFIG_DEBUG_LED, \num
63 * Waiting for SDRAM to set up
66 li $r0, CONFIG_FTSDMC021_BASE
68 lwi $r1, [$r0+FTSDMC021_CR2]
72 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
91 * There are 2 bank connected to FTSMC020 on AG101
92 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
93 * we need to set onboard SDRAM before remap and relocation.
96 write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052
97 write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151
100 * config AHB Controller
103 write32 AHBC_BSR6_A, AHBC_BSR6_D
106 * config PMU controller
108 /* ftpmu010_dlldis_disable, must do it in lowleve_init */
110 setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
113 * config SDRAM controller
116 write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
118 write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
120 write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
123 write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
127 write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
131 write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
140 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
147 #endif /* __NDS32_N1213_43U1H__ */
153 write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
155 /* clear empty BSR registers */
157 li $r4, CONFIG_FTSDMC021_BASE
159 swi $r5, [$r4 + FTSDMC021_BANK1_BSR]
160 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
161 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
163 #ifdef CONFIG_MEM_REMAP
165 * Copy ROM code to SDRAM base for memory remap layout.
166 * This is not the real relocation, the real relocation is the function
167 * relocate_code() is start.S which supports the systems is memory
171 * Doing memory remap is essential for preparing some non-OS or RTOS
174 * This is also a must on ADP-AG101 board.
175 * The reason is because the ROM/FLASH circuit on PCB board.
176 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
177 * ROM/FLASH is used to boot.
179 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
180 * and the FLASH is connected to BANK1.
181 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
182 * and the FLASH is connected to BANK0.
183 * It will occur problem when doing flash probing if the flash is at
184 * BANK0 (0x00000000) while memory remapping was skipped.
186 * Other board like ADP-AG101P may not enable this since there is only
187 * a FLASH connected to bank0.
190 li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
192 la $r1, relo_base /* get $pc or $lp */
194 sethi $r6, hi20(_end)
195 ori $r6, $r6, lo12(_end)
204 * MEM remap bit is operational
205 * - use it to map writeable memory at 0x00000000, in place of flash
206 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
207 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
210 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
212 #endif /* #ifdef CONFIG_MEM_REMAP */
219 li $r8, (CONFIG_DEBUG_LED)
222 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */