2 * Copyright (C) 2011 Andes Technology Corporation
3 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/macro.h>
14 #include <generated/asm-offsets.h>
17 * parameters for Synopsys DWC DDR2/DDR1 Memory Controller
19 #define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE)
20 #define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR)
21 #define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR)
22 #define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR)
23 #define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR)
24 #define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR)
25 #define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0)
26 #define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1)
27 #define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2)
28 #define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3)
29 #define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4)
30 #define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5)
31 #define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6)
32 #define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7)
33 #define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8)
34 #define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9)
35 #define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0)
36 #define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0)
37 #define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR)
38 #define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR)
40 #define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR
41 #define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2
42 #define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR
43 #define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR
44 #define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR
45 #define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR
46 #define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0
47 #define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0
48 #define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR
49 #define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR
51 #define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */
54 * parameters for the ahbc controller
56 #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
57 #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
59 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
62 * parameters for the ANDES PCU controller
64 #define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4)
65 #define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4
68 * numeric 7 segment display
71 write32 CONFIG_DEBUG_LED, \num
75 * Waiting for SDRAM to set up
81 lwi $r1, [$r0+FTSDMC021_CR2]
86 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
101 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
116 write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4
125 * config AHB Controller
128 write32 AHBC_BSR6_A, AHBC_BSR6_D
131 * config Synopsys DWC DDR2/DDR1 Memory Controller
136 write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4
140 * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13
144 write32 DDR2C_IOCR_A, DDR2C_IOCR_D
147 write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812
150 write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D
151 write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D
152 write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D
153 write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D
154 write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D
155 write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D
156 write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D
157 write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D
158 write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D
159 write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D
161 write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040
163 write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf
166 write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000
169 write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852
171 write32 DDR2C_CCR_A, DDR2C_CCR_D
175 write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000
177 /* Wait for ddr init state to be set */
181 /* Wait until the config initialization is finish */
190 ! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004
192 /* Wait for ddr init state to be set */
196 /* wait until the ddr data trainning is complete */
215 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
222 #endif /* __NDS32_N1213_43U1H__ */
227 #ifdef CONFIG_MEM_REMAP
229 * Copy ROM code to SDRAM base for memory remap layout.
230 * This is not the real relocation, the real relocation is the function
231 * relocate_code() is start.S which supports the systems is memory
235 * Doing memory remap is essential for preparing some non-OS or RTOS
238 * This is also a must on ADP-AG101 board.
239 * The reason is because the ROM/FLASH circuit on PCB board.
240 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
241 * ROM/FLASH is used to boot.
243 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
244 * and the FLASH is connected to BANK1.
245 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
246 * and the FLASH is connected to BANK0.
247 * It will occur problem when doing flash probing if the flash is at
248 * BANK0 (0x00000000) while memory remapping was skipped.
250 * Other board like ADP-AG101P may not enable this since there is only
251 * a FLASH connected to bank0.
254 li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
256 la $r1, relo_base /* get $pc or $lp */
258 sethi $r6, hi20(_end)
259 ori $r6, $r6, lo12(_end)
268 * MEM remap bit is operational
269 * - use it to map writeable memory at 0x00000000, in place of flash
270 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
271 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
274 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
276 #endif /* #ifdef CONFIG_MEM_REMAP */
283 * Some of Andes CPU version support FPU coprocessor, if so,
284 * and toolchain support FPU instruction set, we should enable it.
286 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
288 mfsr $r0, $CPU_VER /* enable FPU if it exists */
291 beqz $r0, 1f /* skip if no COP */
292 mfsr $r0, $FUCOP_EXIST
294 beqz $r0, 1f /* skip if no FPU */
304 li $r8, (CONFIG_DEBUG_LED)
307 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */