2 * Copyright (C) 2011 Andes Technology Corporation
3 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/macro.h>
30 #include <generated/asm-offsets.h>
33 * parameters for Synopsys DWC DDR2/DDR1 Memory Controller
35 #define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE)
36 #define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR)
37 #define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR)
38 #define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR)
39 #define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR)
40 #define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR)
41 #define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0)
42 #define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1)
43 #define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2)
44 #define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3)
45 #define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4)
46 #define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5)
47 #define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6)
48 #define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7)
49 #define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8)
50 #define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9)
51 #define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0)
52 #define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0)
53 #define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR)
54 #define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR)
56 #define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR
57 #define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2
58 #define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR
59 #define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR
60 #define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR
61 #define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR
62 #define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0
63 #define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0
64 #define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR
65 #define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR
67 #define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */
70 * parameters for the ahbc controller
72 #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
73 #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
75 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
78 * parameters for the ANDES PCU controller
80 #define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4)
81 #define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4
84 * numeric 7 segment display
87 write32 CONFIG_DEBUG_LED, \num
91 * Waiting for SDRAM to set up
97 lwi $r1, [$r0+FTSDMC021_CR2]
102 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
109 ! jal scale_to_500mhz
117 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
132 write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4
141 * config AHB Controller
144 write32 AHBC_BSR6_A, AHBC_BSR6_D
147 * config Synopsys DWC DDR2/DDR1 Memory Controller
152 write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4
156 * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13
160 write32 DDR2C_IOCR_A, DDR2C_IOCR_D
163 write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812
166 write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D
167 write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D
168 write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D
169 write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D
170 write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D
171 write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D
172 write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D
173 write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D
174 write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D
175 write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D
177 write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040
179 write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf
182 write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000
185 write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852
187 write32 DDR2C_CCR_A, DDR2C_CCR_D
191 write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000
193 /* Wait for ddr init state to be set */
197 /* Wait until the config initialization is finish */
206 ! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004
208 /* Wait for ddr init state to be set */
212 /* wait until the ddr data trainning is complete */
231 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
238 #endif /* __NDS32_N1213_43U1H__ */
243 #ifdef CONFIG_MEM_REMAP
245 * Copy ROM code to SDRAM base for memory remap layout.
246 * This is not the real relocation, the real relocation is the function
247 * relocate_code() is start.S which supports the systems is memory
251 * Doing memory remap is essential for preparing some non-OS or RTOS
254 * This is also a must on ADP-AG101 board.
255 * The reason is because the ROM/FLASH circuit on PCB board.
256 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
257 * ROM/FLASH is used to boot.
259 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
260 * and the FLASH is connected to BANK1.
261 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
262 * and the FLASH is connected to BANK0.
263 * It will occur problem when doing flash probing if the flash is at
264 * BANK0 (0x00000000) while memory remapping was skipped.
266 * Other board like ADP-AG101P may not enable this since there is only
267 * a FLASH connected to bank0.
270 li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
272 la $r1, relo_base /* get $pc or $lp */
274 sethi $r6, hi20(_end)
275 ori $r6, $r6, lo12(_end)
284 * MEM remap bit is operational
285 * - use it to map writeable memory at 0x00000000, in place of flash
286 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
287 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
290 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
292 #endif /* #ifdef CONFIG_MEM_REMAP */
299 * Some of Andes CPU version support FPU coprocessor, if so,
300 * and toolchain support FPU instruction set, we should enable it.
302 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
304 mfsr $r0, $CPU_VER /* enable FPU if it exists */
307 beqz $r0, 1f /* skip if no COP */
308 mfsr $r0, $FUCOP_EXIST
310 beqz $r0, 1f /* skip if no FPU */
320 li $r8, (CONFIG_DEBUG_LED)
323 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */