2 * Andesboot - Startup Code for Whitiger core
4 * Copyright (C) 2006 Andes Technology Corporation
5 * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
6 * Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
7 * Greentime Hu <greentime@andestech.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
15 #include <asm/macro.h>
18 * Jump vector table for EVIC mode
21 #define DIS_DCAC ~ENA_DCAC
22 #define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
23 #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
24 #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
25 #define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
26 #define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
27 #define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
30 #define EIT_INTR_PSW $ir1 ! interruption $PSW
31 #define EIT_PREV_IPSW $ir2 ! previous $IPSW
32 #define EIT_IVB $ir3 ! intr vector base address
33 #define EIT_EVA $ir4 ! MMU related Exception VA reg
34 #define EIT_PREV_EVA $ir5 ! previous $eva
35 #define EIT_ITYPE $ir6 ! interruption type
36 #define EIT_PREV_ITYPE $ir7 ! prev intr type
37 #define EIT_MACH_ERR $ir8 ! machine error log
38 #define EIT_INTR_PC $ir9 ! Interruption PC
39 #define EIT_PREV_IPC $ir10 ! previous $IPC
40 #define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
41 #define EIT_PREV_P0 $ir12 ! prev $P0
42 #define EIT_PREV_P1 $ir13 ! prev $p1
43 #define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
44 #define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
45 #define MR_CAC_CTL $mr8
58 j internal_interrupt ! H0I
59 j internal_interrupt ! H1I
60 j internal_interrupt ! H2I
61 j internal_interrupt ! H3I
62 j internal_interrupt ! H4I
63 j internal_interrupt ! H5I
64 j software_interrupt ! S0I
69 * Andesboot Startup Code (reset vector)
72 * 1.1 reset - start of u-boot
73 * 1.2 to superuser mode - as is when reset
74 * 1.4 Do lowlevel_init
75 * - (this will jump out to lowlevel_init.S in SoC)
77 * 1.3 Turn off watchdog timer
78 * - (this will jump out to watchdog.S in SoC)
79 * - (turnoff_watchdog)
80 * 2. Do critical init when reboot (not from mem)
81 * 3. Relocate andesboot to ram
83 * 5. Jump to second stage (board_init_r)
86 /* Note: TEXT_BASE is defined by the (board-dependent) linker script */
89 .word CONFIG_SYS_TEXT_BASE
92 * These are defined in the board-specific linker script.
93 * Subtracting _start from them lets the linker put their
94 * relative position in the executable instead of leaving
98 /* IRQ stack memory (calculated at run-time) */
99 .globl IRQ_STACK_START
103 /* IRQ stack memory (calculated at run-time) */
104 .globl FIQ_STACK_START
109 /* IRQ stack memory (calculated at run-time) + 8 bytes */
110 .globl IRQ_STACK_START_IN
115 * The bootstrap code of nds32 core
124 /* set IVIC, vector size: 4 bytes, base: 0x0 */
128 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
129 jal load_lowlevel_init
134 * Set the N1213 (Whitiger) core to superuser mode
135 * According to spec, it is already when reset
138 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
139 jal load_turnoff_watchdog
144 * Do CPU critical regs init only at reboot,
145 * not when booting from ram
147 #ifdef CONFIG_INIT_CRITICAL
148 bal cpu_init_crit ! Do CPU critical regs init
152 * Set stackpointer in internal RAM to call board_init_f
153 * $sp must be 8-byte alignment for ABI compliance.
156 li $sp, CONFIG_SYS_INIT_SP_ADDR
157 li $r10, GD_SIZE /* get GD size */
158 sub $sp, $sp, $r10 /* GD start addr */
163 #ifdef __NDS32_N1213_43U1H__
164 /* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
165 la $r15, board_init_f ! store function address into $r15
168 j board_init_f ! jump to board_init_f() in lib/board.c
171 * void relocate_code (addr_sp, gd, addr_moni)
173 * This "function" does not return, instead it continues in RAM
174 * after relocating the monitor code.
179 move $r4, $r0 /* save addr_sp */
180 move $r5, $r1 /* save addr of gd */
181 move $r6, $r2 /* save addr of destination */
183 /* Set up the stack */
189 beq $r0, $r6, clear_bss /* skip relocation */
191 move $r1, $r6 /* r1 <- scratch for copy_loop */
193 sub $r3, $r3, $r0 /* r3 <- __bss_start_ofs */
194 add $r2, $r0, $r3 /* r2 <- source end address */
199 blt $r0, $r2, copy_loop
202 * fix relocations related issues
205 l.w $r0, _TEXT_BASE /* r0 <- Text base */
206 sub $r9, $r6, $r0 /* r9 <- relocation offset */
210 * Now we want to update GOT.
212 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
213 * generated by GNU ld. Skip these reserved entries from relocation.
215 la $r2, __got_start /* r2 <- rel __got_start in FLASH */
216 add $r2, $r2, $r9 /* r2 <- rel __got_start in RAM */
217 la $r3, __got_end /* r3 <- rel __got_end in FLASH */
218 add $r3, $r3, $r9 /* r3 <- rel __got_end in RAM */
219 addi $r2, $r2, #8 /* skipping first two entries */
221 lwi $r0, [$r2] /* r0 <- location in FLASH to fix up */
222 add $r0, $r0, $r9 /* r0 <- location fix up to RAM */
223 swi.p $r0, [$r2], #4 /* r0 <- store fix into .got in RAM */
224 blt $r2, $r3, fix_got_loop
227 la $r0, __bss_start /* r0 <- rel __bss_start in FLASH */
228 add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
229 la $r1, __bss_end /* r1 <- rel __bss_end in RAM */
230 add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
231 li $r2, 0x00000000 /* clear */
234 sw $r2, [$r0] /* clear loop... */
236 bne $r0, $r1, clbss_l
239 * We are done. Do not return, instead branch to second part of board
240 * initialization, now running from RAM.
244 move $lp, $r0 /* offset of board_init_r() */
245 add $lp, $lp, $r9 /* real address of board_init_r() */
246 /* setup parameters for board_init_r */
247 move $r0, $r5 /* gd_t */
248 move $r1, $r6 /* dest_addr */
251 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
252 move $r15, $lp /* store function address into $r15 */
257 jr $lp /* jump to board_init_r() */
260 * Initialize CPU critical registers
262 * 1. Setup control registers
264 * 1.2 Flush cache and TLB
265 * 1.3 Disable MMU and cache
266 * 2. Setup memory timing
271 move $r0, $lp /* push ra */
273 /* Disable Interrupts by clear GIE in $PSW reg */
276 /* Flush caches and TLB */
277 /* Invalidate caches */
283 andi $p0, $p0, 0x3 ! MMPS
284 li $p1, 0x2 ! TLB MMU
286 tlbop flushall ! Flush TLB
289 ! Disable MMU, Dcache
290 ! Whitiger is MMU disabled when reset
292 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
294 and $p0, $p0, $p1 ! Set DC_EN bit
295 mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
302 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
304 la $r6, lowlevel_init
311 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
312 load_turnoff_watchdog:
313 la $r6, turnoff_watchdog
314 la $r7, turnoff_wtdog + 4
324 ! read $cr1(I CAC/MEM cfg. reg.) configuration
325 mfsr $t0, CR_ICAC_MEM
328 andi $p0, $t0, ICAC_MEM_KBF_ISZ
330 ! if $p0=0, then no I CAC existed
331 beqz $p0, end_flush_icache
333 ! get $p0 the index of I$ block
336 ! $t1= bit width of I cache line size(ISZ)
340 sll $t5, $t4, $t1 ! get $t5 cache line size
341 andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
342 addi $t2, $p1, 6 ! $t2= bit width of ISET
343 andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
345 addi $p1, $p1, 1 ! then $p1 is I way number
346 add $t3, $t2, $t1 ! SHIFT
347 sll $p1, $p1, $t3 ! GET the total cache size
350 cctl $p1, L1I_IX_INVAL
359 ! read $cr2(D CAC/MEM cfg. reg.) configuration
360 mfsr $t0, CR_DCAC_MEM
363 andi $p0, $t0, DCAC_MEM_KBF_DSZ
365 ! if $p0=0, then no D CAC existed
366 beqz $p0, end_flush_dcache
368 ! get $p0 the index of D$ block
371 ! $t1= bit width of D cache line size(DSZ)
375 sll $t5, $t4, $t1 ! get $t5 cache line size
376 andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
377 addi $t2, $p1, 6 ! $t2= bit width of DSET
378 andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
380 addi $p1, $p1, 1 ! then $p1 is D way number
381 add $t3, $t2, $t1 ! SHIFT
382 sll $p1, $p1, $t3 ! GET the total cache size
385 cctl $p1, L1D_IX_INVAL
400 ! FIXME: Other way to get PC?
401 ! FIXME: Update according to the newest spec!!
405 mfsr $r28, PSW ! $PSW
407 mfsr $r28, EIT_EVA ! $ir1 $EVA
409 mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
411 mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
413 mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
415 mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
417 mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
419 mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
421 mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
423 mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
425 mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
435 pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
436 addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
442 move $r0, $sp ! To get the kernel stack
443 li $r1, 1 ! Determine interruption type
449 move $r0, $sp ! To get the kernel stack
450 li $r1, 2 ! Determine interruption type
456 move $r0, $sp ! To get the kernel stack
457 li $r1, 3 ! Determine interruption type
463 move $r0, $sp ! To get the kernel stack
464 li $r1, 4 ! Determine interruption type
470 move $r0, $sp ! To get the kernel stack
471 li $r1, 5 ! Determine interruption type
477 move $r0, $sp ! To get the kernel stack
478 li $r1, 6 ! Determine interruption type
484 move $r0, $sp ! To get the kernel stack
485 li $r1, 7 ! Determine interruption type
491 move $r0, $sp ! To get the kernel stack
492 li $r1, 8 ! Determine interruption type
498 move $r0, $sp ! To get the kernel stack
499 li $r1, 9 ! Determine interruption type
505 move $r0, $sp ! To get the kernel stack
506 li $r1, 10 ! Determine interruption type
512 * void reset_cpu(ulong addr);
513 * $r0: input address to jump to
517 /* No need to disable MMU because we never enable it */
522 andi $p0, $p0, 0x3 ! MMPS
523 li $p1, 0x2 ! TLB MMU
525 tlbop flushall ! Flush TLB
527 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
529 and $p0, $p0, $p1 ! Clear the DC_EN bit
530 mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
531 br $r0 ! Jump to the input address