2 * Andesboot - Startup Code for Whitiger core
4 * Copyright (C) 2006 Andes Technology Corporation
5 * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
6 * Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
7 * Greentime Hu <greentime@andestech.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm-offsets.h>
31 #include <asm/macro.h>
35 * Jump vector table for EVIC mode
38 #define DIS_DCAC ~ENA_DCAC
39 #define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
40 #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
41 #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
42 #define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
43 #define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
44 #define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
47 #define EIT_INTR_PSW $ir1 ! interruption $PSW
48 #define EIT_PREV_IPSW $ir2 ! previous $IPSW
49 #define EIT_IVB $ir3 ! intr vector base address
50 #define EIT_EVA $ir4 ! MMU related Exception VA reg
51 #define EIT_PREV_EVA $ir5 ! previous $eva
52 #define EIT_ITYPE $ir6 ! interruption type
53 #define EIT_PREV_ITYPE $ir7 ! prev intr type
54 #define EIT_MACH_ERR $ir8 ! machine error log
55 #define EIT_INTR_PC $ir9 ! Interruption PC
56 #define EIT_PREV_IPC $ir10 ! previous $IPC
57 #define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
58 #define EIT_PREV_P0 $ir12 ! prev $P0
59 #define EIT_PREV_P1 $ir13 ! prev $p1
60 #define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
61 #define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
62 #define MR_CAC_CTL $mr8
75 j internal_interrupt ! H0I
76 j internal_interrupt ! H1I
77 j internal_interrupt ! H2I
78 j internal_interrupt ! H3I
79 j internal_interrupt ! H4I
80 j internal_interrupt ! H5I
81 j software_interrupt ! S0I
86 * Andesboot Startup Code (reset vector)
89 * 1.1 reset - start of u-boot
90 * 1.2 to superuser mode - as is when reset
91 * 1.4 Do lowlevel_init
92 * - (this will jump out to lowlevel_init.S in SoC)
94 * 1.3 Turn off watchdog timer
95 * - (this will jump out to watchdog.S in SoC)
96 * - (turnoff_watchdog)
97 * 2. Do critical init when reboot (not from mem)
98 * 3. Relocate andesboot to ram
100 * 5. Jump to second stage (board_init_r)
103 /* Note: TEXT_BASE is defined by the (board-dependent) linker script */
106 .word CONFIG_SYS_TEXT_BASE
109 * These are defined in the board-specific linker script.
110 * Subtracting _start from them lets the linker put their
111 * relative position in the executable instead of leaving
114 #ifdef CONFIG_USE_IRQ
115 /* IRQ stack memory (calculated at run-time) */
116 .globl IRQ_STACK_START
120 /* IRQ stack memory (calculated at run-time) */
121 .globl FIQ_STACK_START
126 /* IRQ stack memory (calculated at run-time) + 8 bytes */
127 .globl IRQ_STACK_START_IN
132 * The bootstrap code of nds32 core
141 /* set IVIC, vector size: 4 bytes, base: 0x0 */
145 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
146 jal load_lowlevel_init
151 * Set the N1213 (Whitiger) core to superuser mode
152 * According to spec, it is already when reset
155 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
156 jal load_turnoff_watchdog
161 * Do CPU critical regs init only at reboot,
162 * not when booting from ram
164 #ifdef CONFIG_INIT_CRITICAL
165 bal cpu_init_crit ! Do CPU critical regs init
169 * Set stackpointer in internal RAM to call board_init_f
170 * $sp must be 8-byte alignment for ABI compliance.
173 li $sp, CONFIG_SYS_INIT_SP_ADDR
177 #ifdef __NDS32_N1213_43U1H__
178 /* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
179 la $r15, board_init_f ! store function address into $r15
182 j board_init_f ! jump to board_init_f() in lib/board.c
185 * void relocate_code (addr_sp, gd, addr_moni)
187 * This "function" does not return, instead it continues in RAM
188 * after relocating the monitor code.
193 move $r4, $r0 /* save addr_sp */
194 move $r5, $r1 /* save addr of gd */
195 move $r6, $r2 /* save addr of destination */
197 /* Set up the stack */
203 beq $r0, $r6, clear_bss /* skip relocation */
205 move $r1, $r6 /* r1 <- scratch for copy_loop */
207 sub $r3, $r3, $r0 /* r3 <- __bss_start_ofs */
208 add $r2, $r0, $r3 /* r2 <- source end address */
213 blt $r0, $r2, copy_loop
216 * fix relocations related issues
219 l.w $r0, _TEXT_BASE /* r0 <- Text base */
220 sub $r9, $r6, $r0 /* r9 <- relocation offset */
224 * Now we want to update GOT.
226 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
227 * generated by GNU ld. Skip these reserved entries from relocation.
229 la $r2, __got_start /* r2 <- rel __got_start in FLASH */
230 add $r2, $r2, $r9 /* r2 <- rel __got_start in RAM */
231 la $r3, __got_end /* r3 <- rel __got_end in FLASH */
232 add $r3, $r3, $r9 /* r3 <- rel __got_end in RAM */
233 addi $r2, $r2, #8 /* skipping first two entries */
235 lwi $r0, [$r2] /* r0 <- location in FLASH to fix up */
236 add $r0, $r0, $r9 /* r0 <- location fix up to RAM */
237 swi.p $r0, [$r2], #4 /* r0 <- store fix into .got in RAM */
238 blt $r2, $r3, fix_got_loop
241 la $r0, __bss_start /* r0 <- rel __bss_start in FLASH */
242 add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
243 la $r1, __bss_end__ /* r1 <- rel __bss_end in RAM */
244 add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
245 li $r2, 0x00000000 /* clear */
248 sw $r2, [$r0] /* clear loop... */
250 bne $r0, $r1, clbss_l
253 * We are done. Do not return, instead branch to second part of board
254 * initialization, now running from RAM.
258 move $lp, $r0 /* offset of board_init_r() */
259 add $lp, $lp, $r9 /* real address of board_init_r() */
260 /* setup parameters for board_init_r */
261 move $r0, $r5 /* gd_t */
262 move $r1, $r6 /* dest_addr */
265 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
266 move $r15, $lp /* store function address into $r15 */
271 jr $lp /* jump to board_init_r() */
274 * Initialize CPU critical registers
276 * 1. Setup control registers
278 * 1.2 Flush cache and TLB
279 * 1.3 Disable MMU and cache
280 * 2. Setup memory timing
285 move $r0, $lp /* push ra */
287 /* Disable Interrupts by clear GIE in $PSW reg */
290 /* Flush caches and TLB */
291 /* Invalidate caches */
297 andi $p0, $p0, 0x3 ! MMPS
298 li $p1, 0x2 ! TLB MMU
300 tlbop flushall ! Flush TLB
303 ! Disable MMU, Dcache
304 ! Whitiger is MMU disabled when reset
306 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
308 and $p0, $p0, $p1 ! Set DC_EN bit
309 mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
316 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
318 la $r6, lowlevel_init
325 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
326 load_turnoff_watchdog:
327 la $r6, turnoff_watchdog
328 la $r7, turnoff_wtdog + 4
338 ! read $cr1(I CAC/MEM cfg. reg.) configuration
339 mfsr $t0, CR_ICAC_MEM
342 andi $p0, $t0, ICAC_MEM_KBF_ISZ
344 ! if $p0=0, then no I CAC existed
345 beqz $p0, end_flush_icache
347 ! get $p0 the index of I$ block
350 ! $t1= bit width of I cache line size(ISZ)
354 sll $t5, $t4, $t1 ! get $t5 cache line size
355 andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
356 addi $t2, $p1, 6 ! $t2= bit width of ISET
357 andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
359 addi $p1, $p1, 1 ! then $p1 is I way number
360 add $t3, $t2, $t1 ! SHIFT
361 sll $p1, $p1, $t3 ! GET the total cache size
364 cctl $p1, L1I_IX_INVAL
373 ! read $cr2(D CAC/MEM cfg. reg.) configuration
374 mfsr $t0, CR_DCAC_MEM
377 andi $p0, $t0, DCAC_MEM_KBF_DSZ
379 ! if $p0=0, then no D CAC existed
380 beqz $p0, end_flush_dcache
382 ! get $p0 the index of D$ block
385 ! $t1= bit width of D cache line size(DSZ)
389 sll $t5, $t4, $t1 ! get $t5 cache line size
390 andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
391 addi $t2, $p1, 6 ! $t2= bit width of DSET
392 andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
394 addi $p1, $p1, 1 ! then $p1 is D way number
395 add $t3, $t2, $t1 ! SHIFT
396 sll $p1, $p1, $t3 ! GET the total cache size
399 cctl $p1, L1D_IX_INVAL
414 ! FIXME: Other way to get PC?
415 ! FIXME: Update according to the newest spec!!
419 mfsr $r28, PSW ! $PSW
421 mfsr $r28, EIT_EVA ! $ir1 $EVA
423 mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
425 mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
427 mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
429 mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
431 mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
433 mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
435 mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
437 mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
439 mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
449 pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
450 addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
456 move $r0, $sp ! To get the kernel stack
457 li $r1, 1 ! Determine interruption type
463 move $r0, $sp ! To get the kernel stack
464 li $r1, 2 ! Determine interruption type
470 move $r0, $sp ! To get the kernel stack
471 li $r1, 3 ! Determine interruption type
477 move $r0, $sp ! To get the kernel stack
478 li $r1, 4 ! Determine interruption type
484 move $r0, $sp ! To get the kernel stack
485 li $r1, 5 ! Determine interruption type
491 move $r0, $sp ! To get the kernel stack
492 li $r1, 6 ! Determine interruption type
498 move $r0, $sp ! To get the kernel stack
499 li $r1, 7 ! Determine interruption type
505 move $r0, $sp ! To get the kernel stack
506 li $r1, 8 ! Determine interruption type
512 move $r0, $sp ! To get the kernel stack
513 li $r1, 9 ! Determine interruption type
519 move $r0, $sp ! To get the kernel stack
520 li $r1, 10 ! Determine interruption type
526 * void reset_cpu(ulong addr);
527 * $r0: input address to jump to
531 /* No need to disable MMU because we never enable it */
536 andi $p0, $p0, 0x3 ! MMPS
537 li $p1, 0x2 ! TLB MMU
539 tlbop flushall ! Flush TLB
541 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
543 and $p0, $p0, $p1 ! Clear the DC_EN bit
544 mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
545 br $r0 ! Jump to the input address