1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Andesboot - Startup Code for Whitiger core
5 * Copyright (C) 2006 Andes Technology Corporation
6 * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
7 * Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
8 * Greentime Hu <greentime@andestech.com>
13 #include <asm-offsets.h>
16 #include <asm/macro.h>
19 * Jump vector table for EVIC mode
22 #define DIS_DCAC ~ENA_DCAC
23 #define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
24 #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
25 #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
26 #define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
27 #define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
28 #define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
31 #define EIT_INTR_PSW $ir1 ! interruption $PSW
32 #define EIT_PREV_IPSW $ir2 ! previous $IPSW
33 #define EIT_IVB $ir3 ! intr vector base address
34 #define EIT_EVA $ir4 ! MMU related Exception VA reg
35 #define EIT_PREV_EVA $ir5 ! previous $eva
36 #define EIT_ITYPE $ir6 ! interruption type
37 #define EIT_PREV_ITYPE $ir7 ! prev intr type
38 #define EIT_MACH_ERR $ir8 ! machine error log
39 #define EIT_INTR_PC $ir9 ! Interruption PC
40 #define EIT_PREV_IPC $ir10 ! previous $IPC
41 #define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
42 #define EIT_PREV_P0 $ir12 ! prev $P0
43 #define EIT_PREV_P1 $ir13 ! prev $p1
44 #define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
45 #define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
46 #define MR_CAC_CTL $mr8
59 j internal_interrupt ! H0I
60 j internal_interrupt ! H1I
61 j internal_interrupt ! H2I
62 j internal_interrupt ! H3I
63 j internal_interrupt ! H4I
64 j internal_interrupt ! H5I
65 j software_interrupt ! S0I
70 * Andesboot Startup Code (reset vector)
73 * 1.1 reset - start of u-boot
74 * 1.2 to superuser mode - as is when reset
75 * 1.4 Do lowlevel_init
76 * - (this will jump out to lowlevel_init.S in SoC)
78 * 1.3 Turn off watchdog timer
79 * - (this will jump out to watchdog.S in SoC)
80 * - (turnoff_watchdog)
81 * 2. Do critical init when reboot (not from mem)
82 * 3. Relocate andesboot to ram
84 * 5. Jump to second stage (board_init_r)
87 /* Note: TEXT_BASE is defined by the (board-dependent) linker script */
90 .word CONFIG_SYS_TEXT_BASE
92 /* IRQ stack memory (calculated at run-time) + 8 bytes */
93 .globl IRQ_STACK_START_IN
98 * The bootstrap code of nds32 core
104 * gp = ~0 for burn mode
105 * = ~load_address for load mode
109 sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
111 ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
118 /* set IVIC, vector size: 4 bytes, base: 0x0 */
121 * MMU_CTL NTC0 Non-cacheable
132 #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
134 * MMU_CTL NTC0 Cacheable/Write-Back
142 #ifndef CONFIG_SYS_DCACHE_OFF
143 #ifdef CONFIG_ARCH_MAP_SYSMEM
145 * MMU_CTL NTC1 Non-cacheable
152 * MMU_CTL NTM1 mapping for partition 0
161 #if !defined(CONFIG_SYS_ICACHE_OFF)
168 #if !defined(CONFIG_SYS_DCACHE_OFF)
177 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
180 * gp = ~VMA for burn mode
181 * = ~load_address for load mode
185 sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
187 ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
191 * do critical initializations first (shall be in short time)
192 * do self_relocation ASAP.
196 * Set the N1213 (Whitiger) core to superuser mode
197 * According to spec, it is already when reset
199 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
204 * Do CPU critical regs init only at reboot,
205 * not when booting from ram
207 #ifdef CONFIG_INIT_CRITICAL
208 jal cpu_init_crit ! Do CPU critical regs init
212 * Set stackpointer in internal RAM to call board_init_f
213 * $sp must be 8-byte alignment for ABI compliance.
216 li $sp, CONFIG_SYS_INIT_SP_ADDR
218 bal board_init_f_alloc_reserve
220 bal board_init_f_init_reserve
221 #ifdef CONFIG_DEBUG_UART
226 #ifdef __NDS32_N1213_43U1H__
227 /* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
228 la $r15, board_init_f ! store function address into $r15
231 j board_init_f ! jump to board_init_f() in lib/board.c
234 * void relocate_code (addr_sp, gd, addr_moni)
236 * This "function" does not return, instead it continues in RAM
237 * after relocating the monitor code.
242 * gp = ~RAM_SIZE - TEXT_SIZE for burn/load mode
247 move $r4, $r0 /* save addr_sp */
248 move $r5, $r1 /* save addr of gd */
249 move $r6, $r2 /* save addr of destination */
251 /* Set up the stack */
255 la $r0, _start@GOTOFF
256 beq $r0, $r6, clear_bss /* skip relocation */
259 move $r2, $r6 /* r2 <- scratch for copy_loop */
261 lmw.bim $r11, [$r0], $r18
262 smw.bim $r11, [$r2], $r18
263 blt $r0, $r1, copy_loop
265 * fix relocations related issues
268 l.w $r0, _TEXT_BASE@GOTOFF /* r0 <- Text base */
269 sub $r9, $r6, $r0 /* r9 <- relocation offset */
271 la $r7, __rel_dyn_start@GOTOFF
272 add $r7, $r7, $r9 /* r2 <- rel __got_start in RAM */
273 la $r8, __rel_dyn_end@GOTOFF
274 add $r8, $r8, $r9 /* r2 <- rel __got_start in RAM */
275 li $r3, #0x2a /* R_NDS32_RELATIVE */
277 lmw.bim $r0, [$r7], $r2 /* r0,r1,r2 <- adr,type,addend */
287 la $r0, __bss_start@GOTOFF /* r0 <- rel __bss_start in FLASH */
288 add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
289 la $r1, __bss_end@GOTOFF /* r1 <- rel __bss_end in RAM */
290 add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
291 li $r2, 0x00000000 /* clear */
294 sw $r2, [$r0] /* clear loop... */
296 bne $r0, $r1, clbss_l
299 * We are done. Do not return, instead branch to second part of board
300 * initialization, now running from RAM.
303 bal invalidate_icache_all
305 la $r0, board_init_r@GOTOFF
306 move $lp, $r0 /* offset of board_init_r() */
307 add $lp, $lp, $r9 /* real address of board_init_r() */
308 /* setup parameters for board_init_r */
309 move $r0, $r5 /* gd_t */
310 move $r1, $r6 /* dest_addr */
313 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
314 move $r15, $lp /* store function address into $r15 */
319 jr $lp /* jump to board_init_r() */
322 * Initialize CPU critical registers
324 * 1. Setup control registers
326 * 1.2 Flush cache and TLB
327 * 1.3 Disable MMU and cache
328 * 2. Setup memory timing
333 move $r0, $lp /* push ra */
335 /* Disable Interrupts by clear GIE in $PSW reg */
338 /* Flush caches and TLB */
339 /* Invalidate caches */
345 andi $p0, $p0, 0x3 ! MMPS
346 li $p1, 0x2 ! TLB MMU
348 tlbop flushall ! Flush TLB
351 ! Disable MMU, Dcache
352 ! Whitiger is MMU disabled when reset
354 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
356 and $p0, $p0, $p1 ! Set DC_EN bit
357 mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
368 ! read $cr1(I CAC/MEM cfg. reg.) configuration
369 mfsr $t0, CR_ICAC_MEM
372 andi $p0, $t0, ICAC_MEM_KBF_ISZ
374 ! if $p0=0, then no I CAC existed
375 beqz $p0, end_flush_icache
377 ! get $p0 the index of I$ block
380 ! $t1= bit width of I cache line size(ISZ)
384 sll $t5, $t4, $t1 ! get $t5 cache line size
385 andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
386 addi $t2, $p1, 6 ! $t2= bit width of ISET
387 andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
389 addi $p1, $p1, 1 ! then $p1 is I way number
390 add $t3, $t2, $t1 ! SHIFT
391 sll $p1, $p1, $t3 ! GET the total cache size
394 cctl $p1, L1I_IX_INVAL
403 ! read $cr2(D CAC/MEM cfg. reg.) configuration
404 mfsr $t0, CR_DCAC_MEM
407 andi $p0, $t0, DCAC_MEM_KBF_DSZ
409 ! if $p0=0, then no D CAC existed
410 beqz $p0, end_flush_dcache
412 ! get $p0 the index of D$ block
415 ! $t1= bit width of D cache line size(DSZ)
419 sll $t5, $t4, $t1 ! get $t5 cache line size
420 andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
421 addi $t2, $p1, 6 ! $t2= bit width of DSET
422 andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
424 addi $p1, $p1, 1 ! then $p1 is D way number
425 add $t3, $t2, $t1 ! SHIFT
426 sll $p1, $p1, $t3 ! GET the total cache size
429 cctl $p1, L1D_IX_INVAL
444 ! FIXME: Other way to get PC?
445 ! FIXME: Update according to the newest spec!!
449 mfsr $r28, PSW ! $PSW
451 mfsr $r28, EIT_EVA ! $ir1 $EVA
453 mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
455 mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
457 mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
459 mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
461 mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
463 mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
465 mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
467 mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
469 mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
479 pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
480 addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
486 move $r0, $sp ! To get the kernel stack
487 li $r1, 1 ! Determine interruption type
493 move $r0, $sp ! To get the kernel stack
494 li $r1, 2 ! Determine interruption type
500 move $r0, $sp ! To get the kernel stack
501 li $r1, 3 ! Determine interruption type
507 move $r0, $sp ! To get the kernel stack
508 li $r1, 4 ! Determine interruption type
514 move $r0, $sp ! To get the kernel stack
515 li $r1, 5 ! Determine interruption type
521 move $r0, $sp ! To get the kernel stack
522 li $r1, 6 ! Determine interruption type
528 move $r0, $sp ! To get the kernel stack
529 li $r1, 7 ! Determine interruption type
535 move $r0, $sp ! To get the kernel stack
536 li $r1, 8 ! Determine interruption type
542 move $r0, $sp ! To get the kernel stack
543 li $r1, 9 ! Determine interruption type
549 move $r0, $sp ! To get the kernel stack
550 li $r1, 10 ! Determine interruption type
556 * void reset_cpu(ulong addr);
557 * $r0: input address to jump to
561 /* No need to disable MMU because we never enable it */
566 andi $p0, $p0, 0x3 ! MMPS
567 li $p1, 0x2 ! TLB MMU
569 tlbop flushall ! Flush TLB
571 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
573 and $p0, $p0, $p1 ! Clear the DC_EN bit
574 mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
575 br $r0 ! Jump to the input address