2 * Andesboot - Startup Code for Whitiger core
4 * Copyright (C) 2006 Andes Technology Corporation
5 * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
6 * Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
7 * Greentime Hu <greentime@andestech.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm-offsets.h>
17 #include <asm/macro.h>
20 * Jump vector table for EVIC mode
23 #define DIS_DCAC ~ENA_DCAC
24 #define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
25 #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
26 #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
27 #define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
28 #define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
29 #define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
32 #define EIT_INTR_PSW $ir1 ! interruption $PSW
33 #define EIT_PREV_IPSW $ir2 ! previous $IPSW
34 #define EIT_IVB $ir3 ! intr vector base address
35 #define EIT_EVA $ir4 ! MMU related Exception VA reg
36 #define EIT_PREV_EVA $ir5 ! previous $eva
37 #define EIT_ITYPE $ir6 ! interruption type
38 #define EIT_PREV_ITYPE $ir7 ! prev intr type
39 #define EIT_MACH_ERR $ir8 ! machine error log
40 #define EIT_INTR_PC $ir9 ! Interruption PC
41 #define EIT_PREV_IPC $ir10 ! previous $IPC
42 #define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
43 #define EIT_PREV_P0 $ir12 ! prev $P0
44 #define EIT_PREV_P1 $ir13 ! prev $p1
45 #define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
46 #define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
47 #define MR_CAC_CTL $mr8
60 j internal_interrupt ! H0I
61 j internal_interrupt ! H1I
62 j internal_interrupt ! H2I
63 j internal_interrupt ! H3I
64 j internal_interrupt ! H4I
65 j internal_interrupt ! H5I
66 j software_interrupt ! S0I
71 * Andesboot Startup Code (reset vector)
74 * 1.1 reset - start of u-boot
75 * 1.2 to superuser mode - as is when reset
76 * 1.4 Do lowlevel_init
77 * - (this will jump out to lowlevel_init.S in SoC)
79 * 1.3 Turn off watchdog timer
80 * - (this will jump out to watchdog.S in SoC)
81 * - (turnoff_watchdog)
82 * 2. Do critical init when reboot (not from mem)
83 * 3. Relocate andesboot to ram
85 * 5. Jump to second stage (board_init_r)
88 /* Note: TEXT_BASE is defined by the (board-dependent) linker script */
91 .word CONFIG_SYS_TEXT_BASE
93 /* IRQ stack memory (calculated at run-time) + 8 bytes */
94 .globl IRQ_STACK_START_IN
99 * The bootstrap code of nds32 core
105 * gp = ~0 for burn mode
106 * = ~load_address for load mode
110 sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
112 ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
119 /* set IVIC, vector size: 4 bytes, base: 0x0 */
122 * MMU_CTL NTC0 Non-cacheable
133 #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
135 * MMU_CTL NTC0 Cacheable/Write-Back
143 #ifndef CONFIG_SYS_DCACHE_OFF
144 #ifdef CONFIG_ARCH_MAP_SYSMEM
146 * MMU_CTL NTC1 Non-cacheable
153 * MMU_CTL NTM1 mapping for partition 0
162 #if !defined(CONFIG_SYS_ICACHE_OFF)
169 #if !defined(CONFIG_SYS_DCACHE_OFF)
178 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
181 * gp = ~VMA for burn mode
182 * = ~load_address for load mode
186 sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
188 ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
192 * do critical initializations first (shall be in short time)
193 * do self_relocation ASAP.
197 * Set the N1213 (Whitiger) core to superuser mode
198 * According to spec, it is already when reset
200 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
205 * Do CPU critical regs init only at reboot,
206 * not when booting from ram
208 #ifdef CONFIG_INIT_CRITICAL
209 jal cpu_init_crit ! Do CPU critical regs init
213 * Set stackpointer in internal RAM to call board_init_f
214 * $sp must be 8-byte alignment for ABI compliance.
217 li $sp, CONFIG_SYS_INIT_SP_ADDR
219 bal board_init_f_alloc_reserve
221 bal board_init_f_init_reserve
222 #ifdef CONFIG_DEBUG_UART
227 #ifdef __NDS32_N1213_43U1H__
228 /* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
229 la $r15, board_init_f ! store function address into $r15
232 j board_init_f ! jump to board_init_f() in lib/board.c
235 * void relocate_code (addr_sp, gd, addr_moni)
237 * This "function" does not return, instead it continues in RAM
238 * after relocating the monitor code.
243 * gp = ~RAM_SIZE - TEXT_SIZE for burn/load mode
248 move $r4, $r0 /* save addr_sp */
249 move $r5, $r1 /* save addr of gd */
250 move $r6, $r2 /* save addr of destination */
252 /* Set up the stack */
256 la $r0, _start@GOTOFF
257 beq $r0, $r6, clear_bss /* skip relocation */
260 move $r2, $r6 /* r2 <- scratch for copy_loop */
262 lmw.bim $r11, [$r0], $r18
263 smw.bim $r11, [$r2], $r18
264 blt $r0, $r1, copy_loop
266 * fix relocations related issues
269 l.w $r0, _TEXT_BASE@GOTOFF /* r0 <- Text base */
270 sub $r9, $r6, $r0 /* r9 <- relocation offset */
272 la $r7, __rel_dyn_start@GOTOFF
273 add $r7, $r7, $r9 /* r2 <- rel __got_start in RAM */
274 la $r8, __rel_dyn_end@GOTOFF
275 add $r8, $r8, $r9 /* r2 <- rel __got_start in RAM */
276 li $r3, #0x2a /* R_NDS32_RELATIVE */
278 lmw.bim $r0, [$r7], $r2 /* r0,r1,r2 <- adr,type,addend */
288 la $r0, __bss_start@GOTOFF /* r0 <- rel __bss_start in FLASH */
289 add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
290 la $r1, __bss_end@GOTOFF /* r1 <- rel __bss_end in RAM */
291 add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
292 li $r2, 0x00000000 /* clear */
295 sw $r2, [$r0] /* clear loop... */
297 bne $r0, $r1, clbss_l
300 * We are done. Do not return, instead branch to second part of board
301 * initialization, now running from RAM.
304 bal invalidate_icache_all
306 la $r0, board_init_r@GOTOFF
307 move $lp, $r0 /* offset of board_init_r() */
308 add $lp, $lp, $r9 /* real address of board_init_r() */
309 /* setup parameters for board_init_r */
310 move $r0, $r5 /* gd_t */
311 move $r1, $r6 /* dest_addr */
314 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
315 move $r15, $lp /* store function address into $r15 */
320 jr $lp /* jump to board_init_r() */
323 * Initialize CPU critical registers
325 * 1. Setup control registers
327 * 1.2 Flush cache and TLB
328 * 1.3 Disable MMU and cache
329 * 2. Setup memory timing
334 move $r0, $lp /* push ra */
336 /* Disable Interrupts by clear GIE in $PSW reg */
339 /* Flush caches and TLB */
340 /* Invalidate caches */
346 andi $p0, $p0, 0x3 ! MMPS
347 li $p1, 0x2 ! TLB MMU
349 tlbop flushall ! Flush TLB
352 ! Disable MMU, Dcache
353 ! Whitiger is MMU disabled when reset
355 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
357 and $p0, $p0, $p1 ! Set DC_EN bit
358 mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
369 ! read $cr1(I CAC/MEM cfg. reg.) configuration
370 mfsr $t0, CR_ICAC_MEM
373 andi $p0, $t0, ICAC_MEM_KBF_ISZ
375 ! if $p0=0, then no I CAC existed
376 beqz $p0, end_flush_icache
378 ! get $p0 the index of I$ block
381 ! $t1= bit width of I cache line size(ISZ)
385 sll $t5, $t4, $t1 ! get $t5 cache line size
386 andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
387 addi $t2, $p1, 6 ! $t2= bit width of ISET
388 andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
390 addi $p1, $p1, 1 ! then $p1 is I way number
391 add $t3, $t2, $t1 ! SHIFT
392 sll $p1, $p1, $t3 ! GET the total cache size
395 cctl $p1, L1I_IX_INVAL
404 ! read $cr2(D CAC/MEM cfg. reg.) configuration
405 mfsr $t0, CR_DCAC_MEM
408 andi $p0, $t0, DCAC_MEM_KBF_DSZ
410 ! if $p0=0, then no D CAC existed
411 beqz $p0, end_flush_dcache
413 ! get $p0 the index of D$ block
416 ! $t1= bit width of D cache line size(DSZ)
420 sll $t5, $t4, $t1 ! get $t5 cache line size
421 andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
422 addi $t2, $p1, 6 ! $t2= bit width of DSET
423 andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
425 addi $p1, $p1, 1 ! then $p1 is D way number
426 add $t3, $t2, $t1 ! SHIFT
427 sll $p1, $p1, $t3 ! GET the total cache size
430 cctl $p1, L1D_IX_INVAL
445 ! FIXME: Other way to get PC?
446 ! FIXME: Update according to the newest spec!!
450 mfsr $r28, PSW ! $PSW
452 mfsr $r28, EIT_EVA ! $ir1 $EVA
454 mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
456 mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
458 mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
460 mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
462 mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
464 mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
466 mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
468 mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
470 mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
480 pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
481 addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
487 move $r0, $sp ! To get the kernel stack
488 li $r1, 1 ! Determine interruption type
494 move $r0, $sp ! To get the kernel stack
495 li $r1, 2 ! Determine interruption type
501 move $r0, $sp ! To get the kernel stack
502 li $r1, 3 ! Determine interruption type
508 move $r0, $sp ! To get the kernel stack
509 li $r1, 4 ! Determine interruption type
515 move $r0, $sp ! To get the kernel stack
516 li $r1, 5 ! Determine interruption type
522 move $r0, $sp ! To get the kernel stack
523 li $r1, 6 ! Determine interruption type
529 move $r0, $sp ! To get the kernel stack
530 li $r1, 7 ! Determine interruption type
536 move $r0, $sp ! To get the kernel stack
537 li $r1, 8 ! Determine interruption type
543 move $r0, $sp ! To get the kernel stack
544 li $r1, 9 ! Determine interruption type
550 move $r0, $sp ! To get the kernel stack
551 li $r1, 10 ! Determine interruption type
557 * void reset_cpu(ulong addr);
558 * $r0: input address to jump to
562 /* No need to disable MMU because we never enable it */
567 andi $p0, $p0, 0x3 ! MMPS
568 li $p1, 0x2 ! TLB MMU
570 tlbop flushall ! Flush TLB
572 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
574 and $p0, $p0, $p1 ! Clear the DC_EN bit
575 mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
576 br $r0 ! Jump to the input address