2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
6 * Scott McNutt <smcnutt@psyent.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/types.h>
32 #include <asm/ptrace.h>
36 #ifdef CONFIG_STATUS_LED
37 #include <status_led.h>
40 #if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ)
41 #error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation)
44 /****************************************************************************/
47 interrupt_handler_t *handler;
52 static struct irq_action vecs[32];
54 /*************************************************************************/
55 volatile ulong timestamp = 0;
57 void reset_timer (void)
59 nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
61 /* From Embedded Peripherals Handbook:
63 * "When the hardware is configured with Writeable period
64 * disabled, writing to one of the period_n registers causes
65 * the counter to reset to the fixed Timeout Period specified
66 * at system generation time."
68 * Here we force a reload to prevent early timeouts from
69 * get_timer() when the interrupt period is greater than
72 * Simply write to periodl with its own value to force an
73 * internal counter reload, THEN reset the timestamp.
75 writel (readl (&tmr->periodl), &tmr->periodl);
78 /* From Embedded Peripherals Handbook:
80 * "Writing to one of the period_n registers stops the internal
81 * counter, except when the hardware is configured with Start/Stop
82 * control bits off. If Start/Stop control bits is off, writing
83 * either register does not stop the counter."
85 * In order to accomodate either configuration, the control
86 * register is re-written. If the counter is stopped, it will
87 * be restarted. If it is running, the write is essentially
90 writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
95 ulong get_timer (ulong base)
98 return (timestamp - base);
102 * This function is derived from Blackfin code (read timebase as long long).
103 * On Nios2 it just returns the timer value.
105 unsigned long long get_ticks(void)
111 * This function is derived from Blackfin code.
112 * On Nios2 it returns the number of timer ticks per second.
114 ulong get_tbclk(void)
118 tbclk = CONFIG_SYS_HZ;
122 /* The board must handle this interrupt if a timer is not
125 #if defined(CONFIG_SYS_NIOS_TMRBASE)
126 void tmr_isr (void *arg)
128 nios_timer_t *tmr = (nios_timer_t *)arg;
129 /* Interrupt is cleared by writing anything to the
132 writel (0, &tmr->status);
133 timestamp += CONFIG_SYS_NIOS_TMRMS;
134 #ifdef CONFIG_STATUS_LED
135 status_led_tick(timestamp);
139 static void tmr_init (void)
141 nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
143 writel (0, &tmr->status);
144 writel (0, &tmr->control);
145 writel (NIOS_TIMER_STOP, &tmr->control);
147 #if defined(CONFIG_SYS_NIOS_TMRCNT)
148 writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl);
149 writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh);
151 writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
153 irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
156 #endif /* CONFIG_SYS_NIOS_TMRBASE */
158 /*************************************************************************/
159 int disable_interrupts (void)
161 int val = rdctl (CTL_STATUS);
162 wrctl (CTL_STATUS, val & ~STATUS_IE);
163 return (val & STATUS_IE);
166 void enable_interrupts( void )
168 int val = rdctl (CTL_STATUS);
169 wrctl (CTL_STATUS, val | STATUS_IE);
172 void external_interrupt (struct pt_regs *regs)
175 struct irq_action *act;
177 /* Evaluate only irqs that are both enabled AND pending */
178 irqs = rdctl (CTL_IENABLE) & rdctl (CTL_IPENDING);
181 /* Assume (as does the Nios2 HAL) that bit 0 is highest
182 * priority. NOTE: There is ALWAYS a handler assigned
183 * (the default if no other).
187 act->handler (act->arg);
195 static void def_hdlr (void *arg)
197 unsigned irqs = rdctl (CTL_IENABLE);
199 /* Disable the individual interrupt -- with gratuitous
202 irqs &= ~(1 << (int)arg);
203 wrctl (CTL_IENABLE, irqs);
204 printf ("WARNING: Disabling unhandled interrupt: %d\n",
208 /*************************************************************************/
209 void irq_install_handler (int irq, interrupt_handler_t *hdlr, void *arg)
213 struct irq_action *act;
214 unsigned ena = rdctl (CTL_IENABLE);
216 if ((irq < 0) || (irq > 31))
220 flag = disable_interrupts ();
224 ena |= (1 << irq); /* enable */
226 act->handler = def_hdlr;
227 act->arg = (void *)irq;
228 ena &= ~(1 << irq); /* disable */
230 wrctl (CTL_IENABLE, ena);
231 if (flag) enable_interrupts ();
235 int interrupt_init (void)
239 /* Assign the default handler to all */
240 for (i = 0; i < 32; i++) {
241 vecs[i].handler = def_hdlr;
242 vecs[i].arg = (void *)i;
246 #if defined(CONFIG_SYS_NIOS_TMRBASE)
250 enable_interrupts ();
255 /*************************************************************************/
256 #if defined(CONFIG_CMD_IRQ)
257 int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
260 struct irq_action *act = vecs;
262 printf ("\nInterrupt-Information:\n\n");
263 printf ("Nr Routine Arg Count\n");
264 printf ("-----------------------------\n");
266 for (i=0; i<32; i++) {
267 if (act->handler != def_hdlr) {
268 printf ("%02d %08lx %08lx %d\n",