2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
13 * icache and dcache configuration used only for start.S.
14 * the values are chosen so that it will work for all configuration.
16 #define ICACHE_LINE_SIZE 32 /* fixed 32 */
17 #define ICACHE_SIZE_MAX 0x10000 /* 64k max */
18 #define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */
19 #define DCACHE_SIZE_MAX 0x10000 /* 64k max */
23 .global _start, _except_start, _except_end
26 wrctl status, r0 /* Disable interrupts */
28 * ICACHE INIT -- only the icache line at the reset address
29 * is invalidated at reset. So the init must stay within
30 * the cache line size (8 words). If GERMS is used, we'll
31 * just be invalidating the cache a second time. If cache
32 * is not implemented initi behaves as nop.
34 ori r4, r0, %lo(ICACHE_LINE_SIZE)
35 movhi r5, %hi(ICACHE_SIZE_MAX)
36 ori r5, r5, %lo(ICACHE_SIZE_MAX)
40 br _except_end /* Skip the tramp */
43 * EXCEPTION TRAMPOLINE -- the following gets copied
44 * to the exception address (below), but is otherwise at the
45 * default exception vector offset (0x0020).
48 movhi et, %hi(_exception)
49 ori et, et, %lo(_exception)
54 * INTERRUPTS -- for now, all interrupts masked and globally
57 wrctl ienable, r0 /* All disabled */
60 * DCACHE INIT -- if dcache not implemented, initd behaves as
63 ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
64 movhi r5, %hi(DCACHE_SIZE_MAX)
65 ori r5, r5, %lo(DCACHE_SIZE_MAX)
72 * RELOCATE CODE, DATA & COMMAND TABLE -- the following code
73 * assumes code, data and the command table are all
74 * contiguous. This lets us relocate everything as a single
75 * block. Make sure the linker script matches this ;-)
78 _cur: movhi r5, %hi(_cur - _start)
79 ori r5, r5, %lo(_cur - _start)
80 sub r4, r4, r5 /* r4 <- cur _start */
83 ori r5, r5, %lo(_start) /* r5 <- linked _start */
84 mov sp, r5 /* initial stack below u-boot code */
87 movhi r6, %hi(CONFIG_SYS_MONITOR_LEN)
88 ori r6, r6, %lo(CONFIG_SYS_MONITOR_LEN)
97 /* JUMP TO RELOC ADDR */
99 ori r4, r4, %lo(_reloc)
103 /* STACK INIT -- zero top two words for call back chain. */
109 #ifdef CONFIG_DEBUG_UART
110 /* Set up the debug UART */
111 movhi r2, %hi(debug_uart_init@h)
112 ori r2, r2, %lo(debug_uart_init@h)
116 /* Allocate and initialize reserved area, update SP */
118 movhi r2, %hi(board_init_f_alloc_reserve@h)
119 ori r2, r2, %lo(board_init_f_alloc_reserve@h)
123 movhi r2, %hi(board_init_f_init_reserve@h)
124 ori r2, r2, %lo(board_init_f_init_reserve@h)
127 /* Update frame-pointer */
130 /* Call board_init_f -- never returns */
132 movhi r2, %hi(board_init_f@h)
133 ori r2, r2, %lo(board_init_f@h)
137 * NEVER RETURNS -- but branch to the _start just
143 * relocate_code -- Nios2 handles the relocation above. But
144 * the generic board code monkeys with the heap, stack, etc.
145 * (it makes some assumptions that may not be appropriate
146 * for Nios). Nevertheless, we capitulate here.
148 * We'll call the board_init_r from here since this isn't
149 * supposed to return.
151 * void relocate_code (ulong sp, gd_t *global_data,
153 * __attribute__ ((noreturn));
156 .global relocate_code
159 mov sp, r4 /* Set the new sp */
163 * ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
164 * and between __bss_start and __bss_end.
166 movhi r5, %hi(__bss_start)
167 ori r5, r5, %lo(__bss_start)
168 movhi r6, %hi(__bss_end)
169 ori r6, r6, %lo(__bss_end)
177 movhi r8, %hi(board_init_r@h)
178 ori r8, r8, %lo(board_init_r@h)